arm64: dts: rockchip: add cdn-dp node for rk3399

Add a node for the cdn DP controller which is embedded in the rk3399
SoC.

Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Reviewed-by: Guenter Roeck <groeck@chromium.org>
Change-Id: I253bb9b9d6c1b8a407f7c49503ec666bb8b64d4d

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 4298601b0fc588ab0df8e396f01858946f24b01a..891a124ce1bfd9e625dfd618ec331f067aa3c239 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -447,6 +447,46 @@
                };
        };
 
+       cdn_dp: dp@fec00000 {
+               compatible = "rockchip,rk3399-cdn-dp";
+               reg = <0x0 0xfec00000 0x0 0x100000>;
+               interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
+                        <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
+               clock-names = "core-clk", "pclk", "spdif", "grf";
+               assigned-clocks = <&cru SCLK_DP_CORE>;
+               assigned-clock-rates = <100000000>;
+               power-domains = <&power RK3399_PD_HDCP>;
+               phys = <&tcphy0_dp>, <&tcphy1_dp>;
+               resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>,
+                        <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>;
+               reset-names = "spdif", "dptx", "apb", "core";
+               rockchip,grf = <&grf>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               #sound-dai-cells = <1>;
+               status = "disabled";
+
+               ports {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       dp_in: port {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               dp_in_vopb: endpoint@0 {
+                                       reg = <0>;
+                                       remote-endpoint = <&vopb_out_dp>;
+                               };
+
+                               dp_in_vopl: endpoint@1 {
+                                       reg = <1>;
+                                       remote-endpoint = <&vopl_out_dp>;
+                               };
+                       };
+               };
+       };
+
        gic: interrupt-controller@fee00000 {
                compatible = "arm,gic-v3";
                #interrupt-cells = <4>;
@@ -1613,6 +1653,11 @@
                                reg = <2>;
                                remote-endpoint = <&hdmi_in_vopl>;
                        };
+
+                       vopl_out_dp: endpoint@3 {
+                               reg = <3>;
+                               remote-endpoint = <&dp_in_vopl>;
+                       };
                };
        };
 
@@ -1666,6 +1711,11 @@
                                reg = <2>;
                                remote-endpoint = <&hdmi_in_vopb>;
                        };
+
+                       vopb_out_dp: endpoint@3 {
+                               reg = <3>;
+                               remote-endpoint = <&dp_in_vopb>;
+                       };
                };
        };