phy: rockchip-inno-mipi-dphy: Add reset control for PHY APB

Change-Id: I02915f0c5a291a1aa13c7e3ed45421667a19940d
Signed-off-by: WeiYong Bi <bivvy.bi@rock-chips.com>

diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-inno-mipi-dphy.txt b/Documentation/devicetree/bindings/phy/phy-rockchip-inno-mipi-dphy.txt
index 238e3405f8ebd1883521ad7952acb2307d5fe373..94f4423442e5dd6047870e5c4b4329ba20ff9b96 100644 (file)
--- a/Documentation/devicetree/bindings/phy/phy-rockchip-inno-mipi-dphy.txt
+++ b/Documentation/devicetree/bindings/phy/phy-rockchip-inno-mipi-dphy.txt
@@ -12,6 +12,10 @@ Required properties:
  - rockchip,dsi-panel : phandle to MIPI DSI panel node, used to get the display
                        timing of the panel provided to the PHY module.
 
+Optional properties
+ - resets : phandle to the reset of MIPI DSI PHY APB clock.
+ - reset-names : should be "apb".
+
 Example:
 
 For Rockchip RK3368
@@ -22,6 +26,8 @@ mipi_dphy: mipi-dphy@ff968000 {
        #phy-cells = <0>;
        clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX0>;
        clock-names = "ref", "pclk";
+       resets = <&cru SRST_MIPIDPHYTX>;
+       reset-names = "apb";
        rockchip,dsi-panel = <&dsi_panel>;
 };
 

diff --git a/drivers/phy/phy-rockchip-inno-mipi-dphy.c b/drivers/phy/phy-rockchip-inno-mipi-dphy.c
index 9a3a670d3154a187ca9fe1d4e12ecfbdccd8ec31..6d47458399963bf13fc82a7ce96fe696117ac2ec 100644 (file)
--- a/drivers/phy/phy-rockchip-inno-mipi-dphy.c
+++ b/drivers/phy/phy-rockchip-inno-mipi-dphy.c
@@ -20,6 +20,7 @@
 #include <linux/phy/phy.h>
 #include <linux/platform_device.h>
 #include <linux/regmap.h>
+#include <linux/reset.h>
 
 #include <drm/drm_mipi_dsi.h>
 
@@ -236,6 +237,7 @@ struct inno_mipi_dphy {
        void __iomem *regs;
        struct clk *ref_clk;
        struct clk *pclk;
+       struct reset_control *rst;
 
        struct dsi_panel *panel;
        u32 lanes;
@@ -560,6 +562,13 @@ static int inno_mipi_dphy_power_on(struct phy *phy)
        clk_prepare_enable(inno->ref_clk);
        clk_prepare_enable(inno->pclk);
 
+       if (inno->rst) {
+               /* MIPI DSI PHY APB software reset request. */
+               reset_control_assert(inno->rst);
+               usleep_range(20, 40);
+               reset_control_deassert(inno->rst);
+       }
+
        inno_mipi_dphy_pll_init(inno);
        inno_mipi_dphy_pll_ldo_enable(inno);
        inno_mipi_dphy_lane_enable(inno);
@@ -693,11 +702,19 @@ static int inno_mipi_dphy_probe(struct platform_device *pdev)
                return PTR_ERR(inno->ref_clk);
        }
 
+       clk_set_rate(inno->ref_clk, 24000000);
+
        inno->pclk = devm_clk_get(&pdev->dev, "pclk");
        if (IS_ERR(inno->pclk)) {
                dev_err(&pdev->dev, "failed to get mipi dphy pclk\n");
                return PTR_ERR(inno->pclk);
-       };
+       }
+
+       inno->rst = devm_reset_control_get_optional(&pdev->dev, "apb");
+       if (IS_ERR(inno->rst)) {
+               dev_info(&pdev->dev, "No reset control specified\n");
+               inno->rst = NULL;
+       }
 
        phy = devm_phy_create(&pdev->dev, NULL, &inno_mipi_dphy_ops);
        if (IS_ERR(phy)) {