clk: rockchip: remove more CLK_IGNORE_UNUSED for rk3399 clocktree
authorJianqun Xu <jay.xu@rock-chips.com>
Wed, 2 Nov 2016 07:36:30 +0000 (15:36 +0800)
committerHuang, Tao <huangtao@rock-chips.com>
Tue, 15 Nov 2016 14:10:37 +0000 (22:10 +0800)
Optimize rk3399 clocktree by removing CLK_IGNORE_UNUSED of some clocks.

clocks will managered by usb:
- clk_usbphy0_480m_src
- clk_usbphy1_480m_src
- clk_usbphy_480m

clocks will be managered by pvtm:
- clk_pvtm_core_l
- clk_pvtm_core_b
- clk_pvtm_ddr

clocks will be managered by dfi:
- pclk_ddr_mon
- clk_dfimon0_timer
- clk_dfimon1_timer
- aclk_dcf
- pclk_dcf

Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
(am from https://patchwork.kernel.org/patch/9410123/)

Change-Id: I9c32423cafde00fc47673638633ca0c884253f36
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
drivers/clk/rockchip/clk-rk3399.c

index 03fafd0..110aec0 100644 (file)
@@ -435,11 +435,11 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
        GATE(SCLK_USB2PHY1_REF, "clk_usb2phy1_ref", "xin24m", CLK_IGNORE_UNUSED,
                        RK3399_CLKGATE_CON(6), 6, GFLAGS),
 
-       GATE(SCLK_USBPHY0_480M_SRC, "clk_usbphy0_480m_src", "clk_usbphy0_480m", CLK_IGNORE_UNUSED,
+       GATE(SCLK_USBPHY0_480M_SRC, "clk_usbphy0_480m_src", "clk_usbphy0_480m", 0,
                        RK3399_CLKGATE_CON(13), 12, GFLAGS),
-       GATE(SCLK_USBPHY1_480M_SRC, "clk_usbphy1_480m_src", "clk_usbphy1_480m", CLK_IGNORE_UNUSED,
+       GATE(SCLK_USBPHY1_480M_SRC, "clk_usbphy1_480m_src", "clk_usbphy1_480m", 0,
                        RK3399_CLKGATE_CON(13), 12, GFLAGS),
-       MUX(0, "clk_usbphy_480m", mux_usbphy_480m_p, CLK_IGNORE_UNUSED,
+       MUX(0, "clk_usbphy_480m", mux_usbphy_480m_p, 0,
                        RK3399_CLKSEL_CON(14), 6, 1, MFLAGS),
 
        MUX(0, "upll", mux_pll_src_24m_usbphy480m_p, 0,
@@ -700,7 +700,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
 
        GATE(PCLK_CENTER_MAIN_NOC, "pclk_center_main_noc", "pclk_ddr", CLK_IGNORE_UNUSED,
                        RK3399_CLKGATE_CON(18), 10, GFLAGS),
-       GATE(PCLK_DDR_MON, "pclk_ddr_mon", "pclk_ddr", CLK_IGNORE_UNUSED,
+       GATE(PCLK_DDR_MON, "pclk_ddr_mon", "pclk_ddr", 0,
                        RK3399_CLKGATE_CON(18), 12, GFLAGS),
        GATE(PCLK_CIC, "pclk_cic", "pclk_ddr", CLK_IGNORE_UNUSED,
                        RK3399_CLKGATE_CON(18), 15, GFLAGS),
@@ -709,9 +709,9 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
 
        GATE(SCLK_PVTM_DDR, "clk_pvtm_ddr", "xin24m", 0,
                        RK3399_CLKGATE_CON(4), 11, GFLAGS),
-       GATE(SCLK_DFIMON0_TIMER, "clk_dfimon0_timer", "xin24m", CLK_IGNORE_UNUSED,
+       GATE(SCLK_DFIMON0_TIMER, "clk_dfimon0_timer", "xin24m", 0,
                        RK3399_CLKGATE_CON(3), 5, GFLAGS),
-       GATE(SCLK_DFIMON1_TIMER, "clk_dfimon1_timer", "xin24m", CLK_IGNORE_UNUSED,
+       GATE(SCLK_DFIMON1_TIMER, "clk_dfimon1_timer", "xin24m", 0,
                        RK3399_CLKGATE_CON(3), 6, GFLAGS),
 
        /* cci */
@@ -991,7 +991,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
        GATE(SCLK_INTMEM3, "clk_intmem3", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 5, GFLAGS),
        GATE(SCLK_INTMEM4, "clk_intmem4", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 6, GFLAGS),
        GATE(SCLK_INTMEM5, "clk_intmem5", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 7, GFLAGS),
-       GATE(ACLK_DCF, "aclk_dcf", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 8, GFLAGS),
+       GATE(ACLK_DCF, "aclk_dcf", "aclk_perilp0", 0, RK3399_CLKGATE_CON(23), 8, GFLAGS),
        GATE(ACLK_DMAC0_PERILP, "aclk_dmac0_perilp", "aclk_perilp0", 0, RK3399_CLKGATE_CON(25), 5, GFLAGS),
        GATE(ACLK_DMAC1_PERILP, "aclk_dmac1_perilp", "aclk_perilp0", 0, RK3399_CLKGATE_CON(25), 6, GFLAGS),
        GATE(ACLK_PERILP0_NOC, "aclk_perilp0_noc", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 7, GFLAGS),
@@ -1005,7 +1005,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
        GATE(HCLK_PERILP0_NOC, "hclk_perilp0_noc", "hclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 8, GFLAGS),
 
        /* pclk_perilp0 gates */
-       GATE(PCLK_DCF, "pclk_dcf", "pclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 9, GFLAGS),
+       GATE(PCLK_DCF, "pclk_dcf", "pclk_perilp0", 0, RK3399_CLKGATE_CON(23), 9, GFLAGS),
 
        /* crypto */
        COMPOSITE(SCLK_CRYPTO0, "clk_crypto0", mux_pll_src_cpll_gpll_ppll_p, 0,