ARM64: dts: rk3328: add pdm node
authorSugar Zhang <sugar.zhang@rock-chips.com>
Thu, 30 Mar 2017 03:00:34 +0000 (11:00 +0800)
committerHuang, Tao <huangtao@rock-chips.com>
Fri, 31 Mar 2017 02:10:18 +0000 (10:10 +0800)
Change-Id: Ib3ae44d970e889d512cb89a738b2dd633dbc9a7f
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
arch/arm64/boot/dts/rockchip/rk3328.dtsi

index 437b38b..ba0e1b7 100644 (file)
                status = "disabled";
        };
 
                status = "disabled";
        };
 
+       pdm: pdm@ff040000 {
+               compatible = "rockchip,pdm";
+               reg = <0x0 0xff040000 0x0 0x1000>;
+               clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>;
+               clock-names = "pdm_clk", "pdm_hclk";
+               dmas = <&dmac 16>;
+               #dma-cells = <1>;
+               dma-names = "rx";
+               pinctrl-names = "default", "sleep";
+               pinctrl-0 = <&pdmm0_clk
+                            &pdmm0_fsync
+                            &pdmm0_sdi0
+                            &pdmm0_sdi1
+                            &pdmm0_sdi2
+                            &pdmm0_sdi3>;
+               pinctrl-1 = <&pdmm0_sleep>;
+               status = "disabled";
+       };
+
        grf: syscon@ff100000 {
                compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
                reg = <0x0 0xff100000 0x0 0x1000>;
        grf: syscon@ff100000 {
                compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
                reg = <0x0 0xff100000 0x0 0x1000>;
                        };
                };
 
                        };
                };
 
+               pdm-0 {
+                       pdmm0_clk: pdmm0-clk {
+                               rockchip,pins =
+                                       <2 RK_PC2 RK_FUNC_2 &pcfg_pull_none>;
+                       };
+
+                       pdmm0_fsync: pdmm0-fsync {
+                               rockchip,pins =
+                                       <2 RK_PC7 RK_FUNC_2 &pcfg_pull_none>;
+                       };
+
+                       pdmm0_sdi0: pdmm0-sdi0 {
+                               rockchip,pins =
+                                       <2 RK_PC3 RK_FUNC_2 &pcfg_pull_none>;
+                       };
+
+                       pdmm0_sdi1: pdmm0-sdi1 {
+                               rockchip,pins =
+                                       <2 RK_PC4 RK_FUNC_2 &pcfg_pull_none>;
+                       };
+
+                       pdmm0_sdi2: pdmm0-sdi2 {
+                               rockchip,pins =
+                                       <2 RK_PC5 RK_FUNC_2 &pcfg_pull_none>;
+                       };
+
+                       pdmm0_sdi3: pdmm0-sdi3 {
+                               rockchip,pins =
+                                       <2 RK_PC6 RK_FUNC_2 &pcfg_pull_none>;
+                       };
+
+                       pdmm0_sleep: pdmm0-sleep {
+                               rockchip,pins =
+                                       <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>,
+                                       <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>,
+                                       <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>,
+                                       <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
+                                       <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>,
+                                       <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
+                       };
+               };
+
                i2s1 {
                        i2s1_mclk: i2s1-mclk {
                                rockchip,pins =
                i2s1 {
                        i2s1_mclk: i2s1-mclk {
                                rockchip,pins =