arm64: dts: rk3368: modify rksdmmc to dwmmc

Modify rksdmmc to dwmmc, sync with upstream.

Change-Id: I0aabcf47a5fe1b1f564bde2f719d8c1c48debc90
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>

diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
index 91b8f27b6c3c41a028d1f95f6800e81fe357c636..12af2f36fe39089defc802c90bbdaec8efa4f240 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
@@ -400,7 +400,7 @@
                #clock-cells = <0>;
        };
 
                #clock-cells = <0>;
        };
 

-       sdmmc: rksdmmc@ff0c0000 {
+       sdmmc: dwmmc@ff0c0000 {

                compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
                reg = <0x0 0xff0c0000 0x0 0x4000>;
                clock-freq-min-max = <400000 150000000>;
                compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
                reg = <0x0 0xff0c0000 0x0 0x4000>;
                clock-freq-min-max = <400000 150000000>;


@@ -424,7 +424,7 @@
                status = "disabled";
        };
 
                status = "disabled";
        };
 

-       emmc: rksdmmc@ff0f0000 {
+       emmc: dwmmc@ff0f0000 {

                compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
                reg = <0x0 0xff0f0000 0x0 0x4000>;
                clock-freq-min-max = <400000 150000000>;
                compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
                reg = <0x0 0xff0f0000 0x0 0x4000>;
                clock-freq-min-max = <400000 150000000>;