clk: rockchip: rk3399: fix the incorrect name of uart1~3
authorXing Zheng <zhengxing@rock-chips.com>
Thu, 24 Mar 2016 01:52:33 +0000 (09:52 +0800)
committerGerrit Code Review <gerrit@rock-chips.com>
Thu, 24 Mar 2016 02:23:02 +0000 (10:23 +0800)
Change-Id: I32764eb21d31e4527dc90239cb3d4a450f2def6d
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
drivers/clk/rockchip/clk-rk3399.c

index 9caad04df156f0a5b1b3b01896dcc284727bf98e..4c64d2f7eb735045e5acef28ef520aa9502df703 100644 (file)
@@ -602,21 +602,23 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
        COMPOSITE_NOMUX(0, "clk_uart1_div", "clk_uart_src", 0,
                        RK3399_CLKSEL_CON(34), 0, 7, DFLAGS,
                        RK3399_CLKGATE_CON(9), 2, GFLAGS),
-       COMPOSITE_FRACMUX(0, "clk_uart1_frac", "clk_uart1_src", CLK_SET_RATE_PARENT,
+       COMPOSITE_FRACMUX(0, "clk_uart1_frac", "clk_uart1_div", CLK_SET_RATE_PARENT,
                        RK3399_CLKSEL_CON(101), 0,
                        RK3399_CLKGATE_CON(9), 3, GFLAGS,
                        &rk3399_uart1_fracmux),
-       COMPOSITE_NOMUX(0, "clk_uart2_src", "clk_uart_src", 0,
+
+       COMPOSITE_NOMUX(0, "clk_uart2_div", "clk_uart_src", 0,
                        RK3399_CLKSEL_CON(35), 0, 7, DFLAGS,
                        RK3399_CLKGATE_CON(9), 4, GFLAGS),
-       COMPOSITE_FRACMUX(0, "clk_uart2_frac", "clk_uart2_src", CLK_SET_RATE_PARENT,
+       COMPOSITE_FRACMUX(0, "clk_uart2_frac", "clk_uart2_div", CLK_SET_RATE_PARENT,
                        RK3399_CLKSEL_CON(102), 0,
                        RK3399_CLKGATE_CON(9), 5, GFLAGS,
                        &rk3399_uart2_fracmux),
-       COMPOSITE_NOMUX(0, "clk_uart3_src", "clk_uart_src", 0,
+
+       COMPOSITE_NOMUX(0, "clk_uart3_div", "clk_uart_src", 0,
                        RK3399_CLKSEL_CON(36), 0, 7, DFLAGS,
                        RK3399_CLKGATE_CON(9), 6, GFLAGS),
-       COMPOSITE_FRACMUX(0, "clk_uart3_frac", "clk_uart3_src", CLK_SET_RATE_PARENT,
+       COMPOSITE_FRACMUX(0, "clk_uart3_frac", "clk_uart3_div", CLK_SET_RATE_PARENT,
                        RK3399_CLKSEL_CON(103), 0,
                        RK3399_CLKGATE_CON(9), 7, GFLAGS,
                        &rk3399_uart3_fracmux),