UPSTREAM: PCI: rockchip: Mark RC as common clock architecture

The default value of common clock configuration is
zero indicating Rockchip's RC is using asynchronous
clock architecture but actually we are using common
clock. This will confuses some EP drivers if they
need some different settings referring to this value.
So let's fix it.

Change-Id: Idc3bf918db1a0b2366010819972d231cdbceca2d
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
(am from git.kernel.org/cgit/linux/kernel/git/next/linux-next.git
commit f4acd83a6c303ef72a42e9ea2c8c12298d333a66)

diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
index 7d16669b4e7203df4feb64f6245b3c7b932298d8..f204f8b60b00f9c63d50821a143dd09b9dd2f3e9 100644 (file)
--- a/drivers/pci/host/pcie-rockchip.c
+++ b/drivers/pci/host/pcie-rockchip.c
@@ -141,6 +141,7 @@
 #define   PCIE_RC_CONFIG_DCR_CPLS_SHIFT                26
 #define PCIE_RC_CONFIG_LCS             (PCIE_RC_CONFIG_BASE + 0xd0)
 #define   PCIE_RC_CONFIG_LCS_RETRAIN_LINK      BIT(5)
 #define   PCIE_RC_CONFIG_DCR_CPLS_SHIFT                26
 #define PCIE_RC_CONFIG_LCS             (PCIE_RC_CONFIG_BASE + 0xd0)
 #define   PCIE_RC_CONFIG_LCS_RETRAIN_LINK      BIT(5)

+#define   PCIE_RC_CONFIG_LCS_CCC               BIT(6)

 #define   PCIE_RC_CONFIG_LCS_LBMIE             BIT(10)
 #define   PCIE_RC_CONFIG_LCS_LABIE             BIT(11)
 #define   PCIE_RC_CONFIG_LCS_LBMS              BIT(30)
 #define   PCIE_RC_CONFIG_LCS_LBMIE             BIT(10)
 #define   PCIE_RC_CONFIG_LCS_LABIE             BIT(11)
 #define   PCIE_RC_CONFIG_LCS_LBMS              BIT(30)


@@ -536,6 +537,11 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
 
        rockchip_pcie_set_power_limit(rockchip);
 
 
        rockchip_pcie_set_power_limit(rockchip);
 

+       /* Set RC's clock architecture as common clock */
+       status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);
+       status |= PCIE_RC_CONFIG_LCS_CCC;
+       rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
+

        /* Enable Gen1 training */
        rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE,
                            PCIE_CLIENT_CONFIG);
        /* Enable Gen1 training */
        rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE,
                            PCIE_CLIENT_CONFIG);