arm64: dts: rockchip: complete cpufreq config data for rk3328

Change-Id: I422ec388ab6d66e1ba669028d7b88525569e88d5
Signed-off-by: Rocky Hao <rocky.hao@rock-chips.com>

diff --git a/arch/arm64/boot/dts/rockchip/rk3328-evb.dts b/arch/arm64/boot/dts/rockchip/rk3328-evb.dts
index 10a983c1ffdd8eda2843979b688ac9882f126f71..923786c23f87b3b81f817cd9e4d9825444ca72f4 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3328-evb.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3328-evb.dts
@@ -77,6 +77,10 @@
        };
 };
 
+&cpu0 {
+       cpu-supply = <&vdd_arm>;
+};
+
 &emmc {
        bus-width = <8>;
        cap-mmc-highspeed;

diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
index 45d56914f7d3a27a3b406a2cfd1f69e8fbfa65ce..af169ca376fad6be4da376ca341367b5d6256888 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -74,7 +74,7 @@
                        compatible = "arm,cortex-a53", "arm,armv8";
                        reg = <0x0 0x0>;
                        enable-method = "psci";
-//                     clocks = <&cru ARMCLK>;
+                       clocks = <&cru ARMCLK>;
                        operating-points-v2 = <&cpu0_opp_table>;
                };
                cpu1: cpu@1 {
@@ -82,18 +82,21 @@
                        compatible = "arm,cortex-a53", "arm,armv8";
                        reg = <0x0 0x1>;
                        enable-method = "psci";
+                       operating-points-v2 = <&cpu0_opp_table>;
                };
                cpu2: cpu@2 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a53", "arm,armv8";
                        reg = <0x0 0x2>;
                        enable-method = "psci";
+                       operating-points-v2 = <&cpu0_opp_table>;
                };
                cpu3: cpu@3 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a53", "arm,armv8";
                        reg = <0x0 0x3>;
                        enable-method = "psci";
+                       operating-points-v2 = <&cpu0_opp_table>;
                };
        };