ARM64: dts: rk3328: add mali-450 GPU device
authorchenzhen <chenzhen@rock-chips.com>
Mon, 6 Mar 2017 07:49:23 +0000 (15:49 +0800)
committerchenzhen <chenzhen@rock-chips.com>
Wed, 5 Apr 2017 09:15:10 +0000 (17:15 +0800)
GPU and DDR share vdd_logic.
DDR DVFS is not ready yet, to ensure DDR could work stably,
vdd_logic(vdd_gpu) should be higher than 1.05V.
This would be optimized after DDR DVFS is ready.

Change-Id: I2749484c7f6f86dde850f0f85d606e1c1ab85c17
Signed-off-by: chenzhen <chenzhen@rock-chips.com>
arch/arm64/boot/dts/rockchip/rk3328.dtsi

index 920bea1..fdcf719 100644 (file)
                status = "disabled";
        };
 
+       gpu: gpu@ff300000 {
+               compatible = "arm,mali-450";
+               /* first item of 'reg' is dummy, to fit src code. */
+               reg = <0x0 0xff300000 0x0 0x40000>,
+                     <0x0 0xff300000 0x0 0x40000>;
+               interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-names = "Mali_GP_IRQ",
+                                 "Mali_GP_MMU_IRQ",
+                                 "IRQPP",
+                                 "Mali_PP0_IRQ",
+                                 "Mali_PP0_MMU_IRQ",
+                                 "Mali_PP1_IRQ",
+                                 "Mali_PP1_MMU_IRQ";
+               clocks = <&cru ACLK_GPU>;
+               clock-names = "clk_mali";
+               operating-points-v2 = <&gpu_opp_table>;
+               status = "disabled";
+       };
+
+       gpu_opp_table: opp-table2 {
+               compatible = "operating-points-v2";
+
+               opp@200000000 {
+                       opp-hz = /bits/ 64 <200000000>;
+                       opp-microvolt = <1050000>;
+               };
+               opp@300000000 {
+                       opp-hz = /bits/ 64 <300000000>;
+                       opp-microvolt = <1050000>;
+               };
+               opp@400000000 {
+                       opp-hz = /bits/ 64 <400000000>;
+                       opp-microvolt = <1050000>;
+               };
+               opp@500000000 {
+                       opp-hz = /bits/ 64 <500000000>;
+                       opp-microvolt = <1100000>;
+               };
+       };
+
        vop: vop@ff370000 {
                compatible = "rockchip,rk3328-vop";
                reg = <0x0 0xff370000 0x0 0x3efc>;