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inline | side by side (from parent 1:
4c5f4f3)
Change-Id: I855e79023a9e244c2db37af88a075a4ef4c36aec
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
RK3368_CLKSEL_CON(4), 8, 5, DFLAGS,
RK3368_CLKGATE_CON(0), 13, GFLAGS),
RK3368_CLKSEL_CON(4), 8, 5, DFLAGS,
RK3368_CLKGATE_CON(0), 13, GFLAGS),
- COMPOSITE(0, "aclk_cci_pre", mux_pll_src_cpll_gpll_usb_npll_p, CLK_IGNORE_UNUSED,
- RK3368_CLKSEL_CON(5), 6, 2, MFLAGS, 0, 7, DFLAGS,
+ COMPOSITE(ACLK_CCI_PRE, "aclk_cci_pre", mux_pll_src_cpll_gpll_usb_npll_p, CLK_IGNORE_UNUSED,
+ RK3368_CLKSEL_CON(5), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3368_CLKGATE_CON(0), 12, GFLAGS),
GATE(SCLK_PVTM_CORE, "sclk_pvtm_core", "xin24m", 0, RK3368_CLKGATE_CON(7), 10, GFLAGS),
RK3368_CLKGATE_CON(0), 12, GFLAGS),
GATE(SCLK_PVTM_CORE, "sclk_pvtm_core", "xin24m", 0, RK3368_CLKGATE_CON(7), 10, GFLAGS),
#define ACLK_VIDEO 208
#define ACLK_BUS 209
#define ACLK_PERI 210
#define ACLK_VIDEO 208
#define ACLK_BUS 209
#define ACLK_PERI 210
+#define ACLK_CCI_PRE 211
/* pclk gates */
#define PCLK_GPIO0 320
/* pclk gates */
#define PCLK_GPIO0 320