clk: rockchip: add clock ids for efuse on RK3366
authorFinley Xiao <finley.xiao@rock-chips.com>
Wed, 16 Nov 2016 03:46:20 +0000 (11:46 +0800)
committerHuang, Tao <huangtao@rock-chips.com>
Wed, 16 Nov 2016 10:33:39 +0000 (18:33 +0800)
Set the newly added id for efuse, so that they can be called
in other parts.

Change-Id: Id372ca207901aed689304f862412b2cf1e08fa80
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
drivers/clk/rockchip/clk-rk3366.c
include/dt-bindings/clock/rk3366-cru.h

index 2c44dc4..e698998 100644 (file)
@@ -643,8 +643,8 @@ static struct rockchip_clk_branch rk3366_clk_branches[] __initdata = {
        GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus", 0, RK3368_CLKGATE_CON(12), 3, GFLAGS),
        GATE(PCLK_DDRUPCTL, "pclk_ddrupctl", "pclk_bus", 0, RK3368_CLKGATE_CON(12), 13, GFLAGS),
        GATE(PCLK_DDRPHY, "pclk_ddrphy", "pclk_bus", 0, RK3368_CLKGATE_CON(12), 14, GFLAGS),
-       GATE(0, "pclk_efuse_1024", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 0, GFLAGS),
-       GATE(0, "pclk_efuse_256", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 1, GFLAGS),
+       GATE(PCLK_EFUSE_1024, "pclk_efuse_1024", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 0, GFLAGS),
+       GATE(PCLK_EFUSE_256, "pclk_efuse_256", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 1, GFLAGS),
        GATE(PCLK_UART2, "pclk_uart2", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 5, GFLAGS),
        GATE(PCLK_RKPWM, "pclk_rk_pwm", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 6, GFLAGS),
        GATE(0, "pclk_ddrnoc", "pclk_bus", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(13), 10, GFLAGS),
index 0ae3549..31ae399 100644 (file)
 #define PCLK_PERI1             363
 #define PCLK_MIPI_DSI0         364
 #define PCLK_ISP               365
+#define PCLK_EFUSE_1024                366
+#define PCLK_EFUSE_256         367
 
 /* hclk gates */
 #define HCLK_I2S_8CH           448