Documentation: rockchip-emmc-phy: add ctrl-base support
authorShawn Lin <shawn.lin@rock-chips.com>
Mon, 9 May 2016 08:04:59 +0000 (16:04 +0800)
committerHuang, Tao <huangtao@rock-chips.com>
Fri, 13 May 2016 02:38:00 +0000 (10:38 +0800)
This patch adds ctrl-base which points to the digital block
to setup phy pll enabling.

Change-Id: I922dd7574229fda6b2ee51ca6ed1d7852ef87d30
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt

index a962faf..73eda56 100644 (file)
@@ -8,6 +8,7 @@ Required properties:
  - #phy-cells: must be 0
  - reg-offset: PHY configure reg address offset in "general
    register files"
+ - ctrl-base: controller digital block's physical address.
 
 Optional Properties:
  - freq-sel: must match the freq of emmc clock, only support the
@@ -22,5 +23,6 @@ emmcphy: phy {
        compatible = "rockchip,rk3399-emmc-phy";
        rockchip,grf = <&grf>;
        reg-offset = <0xf780>;
+       ctrl-base = <0xfe330000>;
        #phy-cells = <0>;
 };