FROMLIST: arm64: dts: rockchip: add Type-C phy for RK3399

There are 2 Type-C phy on RK3399, they are almost same, except the
address of register. They support USB3.0 Type-C and DisplayPort1.3
Alt Mode on USB Type-C. Register a phy, supply it to USB3 controller
and DP controller.

(am from https://patchwork.kernel.org/patch/9256949/)

Change-Id: I840fbb0cc5e9b95e4d2fa88409ef1a98990dffb7
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 42a0bad7d553e05675920ddd3a5b0e4a85b7c2c7..73f71d946260cf34a7815d2dc6d9b1e27d8bd0cf 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -1349,10 +1349,12 @@
                compatible = "rockchip,rk3399-typec-phy";
                reg = <0x0 0xff7c0000 0x0 0x40000>;
                rockchip,grf = <&grf>;
-               #phy-cells = <0>;
+               #phy-cells = <1>;
                clocks = <&cru SCLK_UPHY0_TCPDCORE>,
                         <&cru SCLK_UPHY0_TCPDPHY_REF>;
                clock-names = "tcpdcore", "tcpdphy-ref";
+               assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
+               assigned-clock-rates = <50000000>;
                resets = <&cru SRST_UPHY0>,
                         <&cru SRST_UPHY0_PIPE_L00>,
                         <&cru SRST_P_UPHY0_TCPHY>;
@@ -1369,10 +1371,12 @@
                compatible = "rockchip,rk3399-typec-phy";
                reg = <0x0 0xff800000 0x0 0x40000>;
                rockchip,grf = <&grf>;
-               #phy-cells = <0>;
+               #phy-cells = <1>;
                clocks = <&cru SCLK_UPHY1_TCPDCORE>,
                         <&cru SCLK_UPHY1_TCPDPHY_REF>;
                clock-names = "tcpdcore", "tcpdphy-ref";
+               assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
+               assigned-clock-rates = <50000000>;
                resets = <&cru SRST_UPHY1>,
                         <&cru SRST_UPHY1_PIPE_L00>,
                         <&cru SRST_P_UPHY1_TCPHY>;