ARM64: dts: rk3399: support for box rev2
authorZhangbin Tong <zebulun.tong@rock-chips.com>
Thu, 29 Dec 2016 06:35:08 +0000 (14:35 +0800)
committerHuang, Tao <huangtao@rock-chips.com>
Fri, 30 Dec 2016 06:02:18 +0000 (14:02 +0800)
rk3399 box rev1 and rev2 use gpio control for enable/disable vdd_cpu_b
rev1 use GPIO1_C1(default pull-down), rev2 use GPIO_C2(default pull-up)

Change-Id: I9ddbcff688905386d2d52f680cbb5f93d6c8d526
Signed-off-by: Zhangbin Tong <zebulun.tong@rock-chips.com>
arch/arm64/boot/dts/rockchip/Makefile
arch/arm64/boot/dts/rockchip/rk3399-box-rev2.dts [new file with mode: 0644]

index 70a77870d6a61dabd781a707e200e4c7b58330b2..09affd843f2d3ac7b78018474fc1fd5a145c0f0c 100644 (file)
@@ -6,6 +6,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-tb-sheep.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-box-808-android.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-box-rev1.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-box-rev1-disvr.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-box-808-android.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-box-rev1.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-box-rev1-disvr.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-box-rev2.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-evb-rev1-android.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-evb-rev1-android-next.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-evb-rev1-cros.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-evb-rev1-android.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-evb-rev1-android-next.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-evb-rev1-cros.dtb
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-box-rev2.dts b/arch/arm64/boot/dts/rockchip/rk3399-box-rev2.dts
new file mode 100644 (file)
index 0000000..ce8843f
--- /dev/null
@@ -0,0 +1,133 @@
+/*
+ * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "rk3399-box.dtsi"
+
+/ {
+       model = "Rockchip RK3399 Board rev2 (BOX)";
+       compatible = "rockchip-box-rev2","rockchip,rk3399-box";
+};
+
+&pinctrl {
+       sdio0 {
+               sdio0_bus1: sdio0-bus1 {
+                       rockchip,pins =
+                               <2 20 RK_FUNC_1 &pcfg_pull_up_20ma>;
+               };
+
+               sdio0_bus4: sdio0-bus4 {
+                       rockchip,pins =
+                               <2 20 RK_FUNC_1 &pcfg_pull_up_20ma>,
+                               <2 21 RK_FUNC_1 &pcfg_pull_up_20ma>,
+                               <2 22 RK_FUNC_1 &pcfg_pull_up_20ma>,
+                               <2 23 RK_FUNC_1 &pcfg_pull_up_20ma>;
+               };
+
+               sdio0_cmd: sdio0-cmd {
+                       rockchip,pins =
+                               <2 24 RK_FUNC_1 &pcfg_pull_up_20ma>;
+               };
+
+               sdio0_clk: sdio0-clk {
+                       rockchip,pins =
+                               <2 25 RK_FUNC_1 &pcfg_pull_none_20ma>;
+               };
+       };
+
+       sdmmc {
+               sdmmc_bus1: sdmmc-bus1 {
+                       rockchip,pins =
+                               <4 8 RK_FUNC_1 &pcfg_pull_up_8ma>;
+               };
+
+               sdmmc_bus4: sdmmc-bus4 {
+                       rockchip,pins =
+                               <4 8 RK_FUNC_1 &pcfg_pull_up_8ma>,
+                               <4 9 RK_FUNC_1 &pcfg_pull_up_8ma>,
+                               <4 10 RK_FUNC_1 &pcfg_pull_up_8ma>,
+                               <4 11 RK_FUNC_1 &pcfg_pull_up_8ma>;
+               };
+
+               sdmmc_clk: sdmmc-clk {
+                       rockchip,pins =
+                               <4 12 RK_FUNC_1 &pcfg_pull_none_18ma>;
+               };
+
+               sdmmc_cmd: sdmmc-cmd {
+                       rockchip,pins =
+                               <4 13 RK_FUNC_1 &pcfg_pull_up_8ma>;
+               };
+       };
+
+       fusb30x {
+               fusb0_int: fusb0-int {
+                       rockchip,pins =
+                               <1 2 RK_FUNC_GPIO &pcfg_pull_up>;
+               };
+       };
+
+       pmic {
+               vsel1_gpio: vsel1-gpio {
+                       rockchip,pins =
+                               <1 18 RK_FUNC_GPIO &pcfg_pull_up>;
+               };
+       };
+};
+
+&i2c4 {
+       status = "okay";
+       fusb0: fusb30x@22 {
+               compatible = "fairchild,fusb302";
+               reg = <0x22>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&fusb0_int>;
+               vbus-5v-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
+               int-n-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
+               status = "okay";
+       };
+};
+
+&vdd_cpu_b {
+       vsel-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>;
+       fcs,suspend-voltage-selector = <0>;
+};