clk: samsung: exynos5433: Add clocks for CMU_PERIC domain
authorChanwoo Choi <cw00.choi@samsung.com>
Mon, 2 Feb 2015 14:23:58 +0000 (23:23 +0900)
committerSylwester Nawrocki <s.nawrocki@samsung.com>
Wed, 4 Feb 2015 17:58:09 +0000 (18:58 +0100)
commitd0f5de6677de4405c9acdb88db7c7cf7b9cc954e
treee5aca1e3b38270b58b8c753492b0daad58c1e16d
parent232364969d8a8a17c52fd9b754d15924abf98d6a
clk: samsung: exynos5433: Add clocks for CMU_PERIC domain

This patch adds missing divider/gate clocks of CMU_PERIC domain
which includes I2S/PCM/SPDIF/PWM/SLIMBUS IPs. The SPI/I2S may use
external input clock which has 'ioclk_*' prefix.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
[ideal.song: Change clk flags of to pclk_gpio_* clk, pclk_gpio_* should be always on]
Signed-off-by: Inha Song <ideal.song@samsung.com>
Acked-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
drivers/clk/samsung/clk-exynos5433.c
include/dt-bindings/clock/exynos5433.h