clk: exynos5433: Fix wrong PMS value of exynos5433_pll_rates
authorChanwoo Choi <cw00.choi@samsung.com>
Mon, 27 Apr 2015 11:36:32 +0000 (20:36 +0900)
committerSylwester Nawrocki <s.nawrocki@samsung.com>
Wed, 29 Apr 2015 12:11:35 +0000 (14:11 +0200)
commit85943d7ea5832afd454b7219ec1d8c2498c4fbcc
treeeeec9d2fea63cc3357385cf7d438c90478034de3
parentb57c93be79e4061b8878315df2f6a239ad967d50
clk: exynos5433: Fix wrong PMS value of exynos5433_pll_rates

This patch fixes the wrong PMS value of exynos5433_pll_rates table
for {ATLAS|APOLLO|MEM0|MEM1|BUS|MFC|MPHY|G3D|DISP|ISP|_PLL.
- 720 MHz (mdiv=360, pdiv=6, sdiv=1) -> 700 MHz (mdiv=175, pdiv=3, sdiv=1)
- 350 MHz (mdiv=360, pdiv=6, sdiv=2) -> (mdiv=350, pdiv=6, sdiv=2)
- 133 MHz (mdiv=552, pdiv=6, sdiv=4) -> (mdiv=532, pdiv=6, sdiv=4)

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
drivers/clk/samsung/clk-exynos5433.c