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(parent: fec2638) | patch
drm/rockchip: hdmi: correct 3328 hdmi phy power up timing
authorZheng Yang <zhengyang@rock-chips.com>
Tue, 13 Jun 2017 02:39:00 +0000 (10:39 +0800)
committerHuang, Tao <huangtao@rock-chips.com>
Thu, 15 Jun 2017 08:13:52 +0000 (16:13 +0800)
commit6d2995671209da44883fa8e8def28103cfd26143
treef04051974ca663d257104b610f6ad036fc8aa003tree | snapshot
parentfec26386312b21cf84bb64d844f26d911a1ef3adcommit | diff
drm/rockchip: hdmi: correct 3328 hdmi phy power up timing

According to spec, TMDS driver should power up between PLL
power up and PLL lock.

There is an mistake of pdata en register, the real register
is reg2 bit0, not reg1 bit0.

Change-Id: I9d2b707cbcfd70b63f4a1a277a85f21b62643d2e
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c diff | blob | history
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