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clk: xgene: Fix divider with non-zero shift value
authorLoc Ho <lho@apm.com>
Thu, 19 Nov 2015 19:20:30 +0000 (12:20 -0700)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Thu, 15 Sep 2016 06:27:39 +0000 (08:27 +0200)
commit4aa1324340dabca412d39ba98de7eabd495af7f0
treecb34b30f440e7da003b7e103f7bcfb51e9b392b6tree | snapshot
parentc6210760f2428690255e1fd91cf084b12e827a0acommit | diff
clk: xgene: Fix divider with non-zero shift value

[ Upstream commit 1382ea631ddddb634850a3795527db0feeff5aaf ]

The X-Gene clock driver missed the divider shift operation when
set the divider value.

Signed-off-by: Loc Ho <lho@apm.com>
Fixes: 308964caeebc ("clk: Add APM X-Gene SoC clock driver")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Sasha Levin <alexander.levin@verizon.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
drivers/clk/clk-xgene.c diff | blob | history
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