FROMLIST: drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range
authorYakir Yang <ykk@rock-chips.com>
Mon, 15 Feb 2016 11:10:11 +0000 (19:10 +0800)
committerHuang, Tao <huangtao@rock-chips.com>
Mon, 21 Mar 2016 11:39:40 +0000 (19:39 +0800)
commit13320df7cf5fdbf02acae95feeb74c7d03bce30b
treea6b30204289cd7097b61928920b5c9cd1fc6ebe8
parentc4cde231897510ead8fe4aec7405d18da6837505
FROMLIST: drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range

Both hsync/vsync polarity and interlace mode can be parsed from
drm display mode, and dynamic_range and ycbcr_coeff can be judge
by the video code.

But presumably Exynos still relies on the DT properties, so take
good use of mode_fixup() in to achieve the compatibility hacks.

(am from https://patchwork.kernel.org/patch/8312791/)

Change-Id: Ia7f37daf40fa2d0516d5c44737ad36b5822c6015
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c