X-Git-Url: http://plrg.eecs.uci.edu/git/?p=firefly-linux-kernel-4.4.55.git;a=blobdiff_plain;f=arch%2Farm64%2Fboot%2Fdts%2Frockchip%2Frk3399.dtsi;h=baeaed53cd4d9eca83c11589aaa8864b009515d6;hp=9c14ed2784f153592a467252465e645b93b718b4;hb=3e7f5b5c515dbc56eb3691126aa7e82a05ce3f09;hpb=8c8b9dc444a7e087dca084bf0f17c71e4a2d5644 diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 9c14ed2784f1..baeaed53cd4d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -49,6 +49,8 @@ #include #include +#include "rk3399-dram-default-timing.dtsi" + / { compatible = "rockchip,rk3399"; @@ -114,10 +116,11 @@ reg = <0x0 0x0>; enable-method = "psci"; #cooling-cells = <2>; /* min followed by max */ - dynamic-power-coefficient = <121>; + dynamic-power-coefficient = <100>; clocks = <&cru ARMCLKL>; - cpu-idle-states = <&cpu_sleep>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; operating-points-v2 = <&cluster0_opp>; + sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>; }; cpu_l1: cpu@1 { @@ -126,8 +129,9 @@ reg = <0x0 0x1>; enable-method = "psci"; clocks = <&cru ARMCLKL>; - cpu-idle-states = <&cpu_sleep>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; operating-points-v2 = <&cluster0_opp>; + sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>; }; cpu_l2: cpu@2 { @@ -136,8 +140,9 @@ reg = <0x0 0x2>; enable-method = "psci"; clocks = <&cru ARMCLKL>; - cpu-idle-states = <&cpu_sleep>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; operating-points-v2 = <&cluster0_opp>; + sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>; }; cpu_l3: cpu@3 { @@ -146,8 +151,9 @@ reg = <0x0 0x3>; enable-method = "psci"; clocks = <&cru ARMCLKL>; - cpu-idle-states = <&cpu_sleep>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; operating-points-v2 = <&cluster0_opp>; + sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>; }; cpu_b0: cpu@100 { @@ -156,10 +162,11 @@ reg = <0x0 0x100>; enable-method = "psci"; #cooling-cells = <2>; /* min followed by max */ - dynamic-power-coefficient = <1068>; + dynamic-power-coefficient = <436>; clocks = <&cru ARMCLKB>; - cpu-idle-states = <&cpu_sleep>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; operating-points-v2 = <&cluster1_opp>; + sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>; }; cpu_b1: cpu@101 { @@ -168,49 +175,63 @@ reg = <0x0 0x101>; enable-method = "psci"; clocks = <&cru ARMCLKB>; - cpu-idle-states = <&cpu_sleep>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; operating-points-v2 = <&cluster1_opp>; + sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>; }; idle-states { entry-method = "psci"; - cpu_sleep: cpu-sleep-0 { + + CPU_SLEEP: cpu-sleep { compatible = "arm,idle-state"; local-timer-stop; arm,psci-suspend-param = <0x0010000>; - entry-latency-us = <350>; - exit-latency-us = <600>; - min-residency-us = <1150>; + entry-latency-us = <120>; + exit-latency-us = <250>; + min-residency-us = <900>; + }; + + CLUSTER_SLEEP: cluster-sleep { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x1010000>; + entry-latency-us = <400>; + exit-latency-us = <500>; + min-residency-us = <2000>; }; }; + + /include/ "rk3399-sched-energy.dtsi" + }; cluster0_opp: opp_table0 { compatible = "operating-points-v2"; opp-shared; - opp00 { + opp@408000000 { opp-hz = /bits/ 64 <408000000>; opp-microvolt = <800000>; clock-latency-ns = <40000>; }; - opp01 { + opp@600000000 { opp-hz = /bits/ 64 <600000000>; opp-microvolt = <800000>; }; - opp02 { + opp@816000000 { opp-hz = /bits/ 64 <816000000>; opp-microvolt = <800000>; }; - opp03 { + opp@1008000000 { opp-hz = /bits/ 64 <1008000000>; opp-microvolt = <875000>; }; - opp04 { + opp@1200000000 { opp-hz = /bits/ 64 <1200000000>; opp-microvolt = <925000>; }; - opp05 { + opp@1416000000 { opp-hz = /bits/ 64 <1416000000>; opp-microvolt = <1025000>; }; @@ -220,40 +241,70 @@ compatible = "operating-points-v2"; opp-shared; - opp00 { + opp@408000000 { opp-hz = /bits/ 64 <408000000>; opp-microvolt = <800000>; clock-latency-ns = <40000>; }; - opp01 { + opp@600000000 { opp-hz = /bits/ 64 <600000000>; opp-microvolt = <800000>; }; - opp02 { + opp@816000000 { opp-hz = /bits/ 64 <816000000>; opp-microvolt = <800000>; }; - opp03 { + opp@1008000000 { opp-hz = /bits/ 64 <1008000000>; opp-microvolt = <850000>; }; - opp04 { + opp@1200000000 { opp-hz = /bits/ 64 <1200000000>; opp-microvolt = <925000>; }; }; + cpu_avs: cpu-avs { + cluster0-avs { + cluster-id = <0>; + min-volt = <800000>; /* uV */ + min-freq = <408000>; /* KHz */ + leakage-adjust-volt = < + /* mA mA uV */ + 0 254 0 + >; + nvmem-cells = <&cpul_leakage>; + nvmem-cell-names = "cpu_leakage"; + }; + cluster1-avs { + cluster-id = <1>; + min-volt = <800000>; /* uV */ + min-freq = <408000>; /* KHz */ + leakage-adjust-volt = < + /* mA mA uV */ + 0 254 0 + >; + nvmem-cells = <&cpub_leakage>; + nvmem-cell-names = "cpu_leakage"; + }; + }; + timer { compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; + interrupts = , + , + , + ; + }; + + pmu_a53 { + compatible = "arm,cortex-a53-pmu"; + interrupts = ; }; - arm-pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = ; + pmu_a72 { + compatible = "arm,cortex-a72-pmu"; + interrupts = ; }; xin24m: xin24m { @@ -272,21 +323,23 @@ dmac_bus: dma-controller@ff6d0000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x0 0xff6d0000 0x0 0x4000>; - interrupts = , - ; + interrupts = , + ; #dma-cells = <1>; clocks = <&cru ACLK_DMAC0_PERILP>; clock-names = "apb_pclk"; + peripherals-req-type-burst; }; dmac_peri: dma-controller@ff6e0000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x0 0xff6e0000 0x0 0x4000>; - interrupts = , - ; + interrupts = , + ; #dma-cells = <1>; clocks = <&cru ACLK_DMAC1_PERILP>; clock-names = "apb_pclk"; + peripherals-req-type-burst; }; }; @@ -294,7 +347,7 @@ compatible = "rockchip,rk3399-gmac"; reg = <0x0 0xfe300000 0x0 0x10000>; rockchip,grf = <&grf>; - interrupts = ; + interrupts = ; interrupt-names = "macirq"; clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>, @@ -306,15 +359,7 @@ "pclk_mac"; resets = <&cru SRST_A_GMAC>; reset-names = "stmmaceth"; - status = "disabled"; - }; - - emmc_phy: phy { - compatible = "rockchip,rk3399-emmc-phy"; - reg-offset = <0xf780>; - #phy-cells = <0>; - rockchip,grf = <&grf>; - ctrl-base = <0xfe330000>; + power-domains = <&power RK3399_PD_GMAC>; status = "disabled"; }; @@ -322,12 +367,13 @@ compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xfe310000 0x0 0x4000>; - interrupts = ; + interrupts = ; clock-freq-min-max = <400000 150000000>; clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; fifo-depth = <0x100>; + power-domains = <&power RK3399_PD_SDIOAUDIO>; status = "disabled"; }; @@ -335,145 +381,148 @@ compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xfe320000 0x0 0x4000>; - interrupts = ; + interrupts = ; clock-freq-min-max = <400000 150000000>; clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; fifo-depth = <0x100>; + power-domains = <&power RK3399_PD_SD>; status = "disabled"; }; sdhci: sdhci@fe330000 { compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1"; reg = <0x0 0xfe330000 0x0 0x10000>; - interrupts = ; - clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>; - clock-names = "clk_xin", "clk_ahb"; + interrupts = ; + arasan,soc-ctl-syscon = <&grf>; assigned-clocks = <&cru SCLK_EMMC>; - assigned-clock-parents = <&cru PLL_CPLL>; assigned-clock-rates = <200000000>; + clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>; + clock-names = "clk_xin", "clk_ahb"; + clock-output-names = "emmc_cardclock"; + #clock-cells = <0>; phys = <&emmc_phy>; phy-names = "phy_arasan"; + power-domains = <&power RK3399_PD_EMMC>; status = "disabled"; }; - usb2phy: usb2phy { - compatible = "rockchip,rk3399-usb-phy"; - rockchip,grf = <&grf>; - #address-cells = <1>; - #size-cells = <0>; - - usb2phy0: usb2-phy0 { - #phy-cells = <0>; - #clock-cells = <0>; - reg = <0xe458>; - }; - - usb2phy1: usb2-phy1 { - #phy-cells = <0>; - #clock-cells = <0>; - reg = <0xe468>; - }; - }; - usb_host0_ehci: usb@fe380000 { compatible = "generic-ehci"; reg = <0x0 0xfe380000 0x0 0x20000>; - interrupts = ; - clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>; - clock-names = "hclk_host0", "hclk_host0_arb"; - phys = <&usb2phy0>; - phy-names = "usb2_phy0"; + interrupts = ; + clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, + <&cru SCLK_USBPHY0_480M_SRC>; + clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m"; + phys = <&u2phy0_host>; + phy-names = "usb"; + power-domains = <&power RK3399_PD_PERIHP>; status = "disabled"; }; usb_host0_ohci: usb@fe3a0000 { compatible = "generic-ohci"; reg = <0x0 0xfe3a0000 0x0 0x20000>; - interrupts = ; - clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>; - clock-names = "hclk_host0", "hclk_host0_arb"; + interrupts = ; + clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, + <&cru SCLK_USBPHY0_480M_SRC>; + clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m"; + phys = <&u2phy0_host>; + phy-names = "usb"; + power-domains = <&power RK3399_PD_PERIHP>; status = "disabled"; }; usb_host1_ehci: usb@fe3c0000 { compatible = "generic-ehci"; reg = <0x0 0xfe3c0000 0x0 0x20000>; - interrupts = ; - clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>; - clock-names = "hclk_host1", "hclk_host1_arb"; - phys = <&usb2phy1>; - phy-names = "usb2_phy1"; + interrupts = ; + clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>, + <&cru SCLK_USBPHY1_480M_SRC>; + clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m"; + phys = <&u2phy1_host>; + phy-names = "usb"; + power-domains = <&power RK3399_PD_PERIHP>; status = "disabled"; }; usb_host1_ohci: usb@fe3e0000 { compatible = "generic-ohci"; reg = <0x0 0xfe3e0000 0x0 0x20000>; - interrupts = ; - clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>; - clock-names = "hclk_host1", "hclk_host1_arb"; + interrupts = ; + clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>, + <&cru SCLK_USBPHY1_480M_SRC>; + clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m"; + phys = <&u2phy1_host>; + phy-names = "usb"; + power-domains = <&power RK3399_PD_PERIHP>; status = "disabled"; }; usbdrd3_0: usb@fe800000 { - compatible = "rockchip,dwc3"; + compatible = "rockchip,rk3399-dwc3"; clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>, - <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>, - <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>; - clock-names = "clk_usb3otg0_ref", "clk_usb3otg0_suspend", - "aclk_usb3otg0", "aclk_usb3_rksoc_axi_perf", - "aclk_usb3", "aclk_usb3_grf"; + <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>; + clock-names = "ref_clk", "suspend_clk", + "bus_clk", "grf_clk"; + power-domains = <&power RK3399_PD_USB3>; + resets = <&cru SRST_A_USB3_OTG0>; + reset-names = "usb3-otg"; #address-cells = <2>; #size-cells = <2>; ranges; status = "disabled"; - usbdrd_dwc3_0: dwc3 { + usbdrd_dwc3_0: dwc3@fe800000 { compatible = "snps,dwc3"; reg = <0x0 0xfe800000 0x0 0x100000>; - interrupts = ; + interrupts = ; dr_mode = "otg"; - tx-fifo-resize; + phys = <&u2phy0_otg>, <&tcphy0_usb3>; + phy-names = "usb2-phy", "usb3-phy"; + phy_type = "utmi_wide"; snps,dis_enblslpm_quirk; - snps,phyif_utmi_16_bits; - snps,dis_u2_freeclk_exists_quirk; - snps,dis_del_phy_power_chg_quirk; - snps,xhci_slow_suspend_quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis_u2_susphy_quirk; + snps,dis-del-phy-power-chg-quirk; + snps,xhci-slow-suspend-quirk; status = "disabled"; }; }; usbdrd3_1: usb@fe900000 { - compatible = "rockchip,dwc3"; + compatible = "rockchip,rk3399-dwc3"; clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>, - <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>, - <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>; - clock-names = "clk_usb3otg1_ref", "clk_usb3otg1_suspend", - "aclk_usb3otg1", "aclk_usb3_rksoc_axi_perf", - "aclk_usb3", "aclk_usb3_grf"; + <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_GRF>; + clock-names = "ref_clk", "suspend_clk", + "bus_clk", "grf_clk"; + power-domains = <&power RK3399_PD_USB3>; + resets = <&cru SRST_A_USB3_OTG1>; + reset-names = "usb3-otg"; #address-cells = <2>; #size-cells = <2>; ranges; status = "disabled"; - usbdrd_dwc3_1: dwc3 { + usbdrd_dwc3_1: dwc3@fe900000 { compatible = "snps,dwc3"; reg = <0x0 0xfe900000 0x0 0x100000>; - interrupts = ; - dr_mode = "otg"; - tx-fifo-resize; + interrupts = ; + dr_mode = "host"; + phys = <&u2phy1_otg>, <&tcphy1_usb3>; + phy-names = "usb2-phy", "usb3-phy"; + phy_type = "utmi_wide"; snps,dis_enblslpm_quirk; - snps,phyif_utmi_16_bits; - snps,dis_u2_freeclk_exists_quirk; - snps,dis_del_phy_power_chg_quirk; - snps,xhci_slow_suspend_quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis_u2_susphy_quirk; + snps,dis-del-phy-power-chg-quirk; + snps,xhci-slow-suspend-quirk; status = "disabled"; }; }; gic: interrupt-controller@fee00000 { compatible = "arm,gic-v3"; - #interrupt-cells = <3>; + #interrupt-cells = <4>; #address-cells = <2>; #size-cells = <2>; ranges; @@ -484,21 +533,33 @@ <0x0 0xfff00000 0 0x10000>, /* GICC */ <0x0 0xfff10000 0 0x10000>, /* GICH */ <0x0 0xfff20000 0 0x10000>; /* GICV */ - interrupts = ; + interrupts = ; its: interrupt-controller@fee20000 { compatible = "arm,gic-v3-its"; msi-controller; reg = <0x0 0xfee20000 0x0 0x20000>; }; + + ppi-partitions { + part0: interrupt-partition-0 { + affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>; + }; + + part1: interrupt-partition-1 { + affinity = <&cpu_b0 &cpu_b1>; + }; + }; }; saradc: saradc@ff100000 { compatible = "rockchip,rk3399-saradc"; reg = <0x0 0xff100000 0x0 0x100>; - interrupts = ; + interrupts = ; #io-channel-cells = <1>; clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; clock-names = "saradc", "apb_pclk"; + resets = <&cru SRST_P_SARADC>; + reset-names = "saradc-apb"; status = "disabled"; }; @@ -507,7 +568,7 @@ reg = <0x0 0xff3c0000 0x0 0x1000>; clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>; clock-names = "i2c", "pclk"; - interrupts = ; + interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&i2c0_xfer>; #address-cells = <1>; @@ -520,7 +581,7 @@ reg = <0x0 0xff110000 0x0 0x1000>; clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; clock-names = "i2c", "pclk"; - interrupts = ; + interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&i2c1_xfer>; #address-cells = <1>; @@ -533,7 +594,7 @@ reg = <0x0 0xff120000 0x0 0x1000>; clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; clock-names = "i2c", "pclk"; - interrupts = ; + interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&i2c2_xfer>; #address-cells = <1>; @@ -546,7 +607,7 @@ reg = <0x0 0xff130000 0x0 0x1000>; clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; clock-names = "i2c", "pclk"; - interrupts = ; + interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&i2c3_xfer>; #address-cells = <1>; @@ -559,7 +620,7 @@ reg = <0x0 0xff140000 0x0 0x1000>; clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>; clock-names = "i2c", "pclk"; - interrupts = ; + interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&i2c5_xfer>; #address-cells = <1>; @@ -572,7 +633,7 @@ reg = <0x0 0xff150000 0x0 0x1000>; clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>; clock-names = "i2c", "pclk"; - interrupts = ; + interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&i2c6_xfer>; #address-cells = <1>; @@ -585,7 +646,7 @@ reg = <0x0 0xff160000 0x0 0x1000>; clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>; clock-names = "i2c", "pclk"; - interrupts = ; + interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&i2c7_xfer>; #address-cells = <1>; @@ -598,7 +659,7 @@ reg = <0x0 0xff180000 0x0 0x100>; clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; clock-names = "baudclk", "apb_pclk"; - interrupts = ; + interrupts = ; reg-shift = <2>; reg-io-width = <4>; pinctrl-names = "default"; @@ -611,7 +672,7 @@ reg = <0x0 0xff190000 0x0 0x100>; clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; clock-names = "baudclk", "apb_pclk"; - interrupts = ; + interrupts = ; reg-shift = <2>; reg-io-width = <4>; pinctrl-names = "default"; @@ -624,7 +685,7 @@ reg = <0x0 0xff1a0000 0x0 0x100>; clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; clock-names = "baudclk", "apb_pclk"; - interrupts = ; + interrupts = ; reg-shift = <2>; reg-io-width = <4>; pinctrl-names = "default"; @@ -637,7 +698,7 @@ reg = <0x0 0xff1b0000 0x0 0x100>; clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; clock-names = "baudclk", "apb_pclk"; - interrupts = ; + interrupts = ; reg-shift = <2>; reg-io-width = <4>; pinctrl-names = "default"; @@ -650,7 +711,7 @@ reg = <0x0 0xff1c0000 0x0 0x1000>; clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; clock-names = "spiclk", "apb_pclk"; - interrupts = ; + interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; #address-cells = <1>; @@ -663,7 +724,7 @@ reg = <0x0 0xff1d0000 0x0 0x1000>; clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; clock-names = "spiclk", "apb_pclk"; - interrupts = ; + interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; #address-cells = <1>; @@ -676,7 +737,7 @@ reg = <0x0 0xff1e0000 0x0 0x1000>; clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; clock-names = "spiclk", "apb_pclk"; - interrupts = ; + interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; #address-cells = <1>; @@ -689,7 +750,7 @@ reg = <0x0 0xff1f0000 0x0 0x1000>; clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>; clock-names = "spiclk", "apb_pclk"; - interrupts = ; + interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>; #address-cells = <1>; @@ -702,7 +763,7 @@ reg = <0x0 0xff200000 0x0 0x1000>; clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>; clock-names = "spiclk", "apb_pclk"; - interrupts = ; + interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>; #address-cells = <1>; @@ -712,9 +773,9 @@ thermal-zones { soc_thermal: soc-thermal { - polling-delay-passive = <100>; /* milliseconds */ + polling-delay-passive = <20>; /* milliseconds */ polling-delay = <1000>; /* milliseconds */ - sustainable-power = <2600>; /* milliwatts */ + sustainable-power = <1000>; /* milliwatts */ thermal-sensors = <&tsadc 0>; @@ -741,16 +802,19 @@ trip = <&target>; cooling-device = <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <4096>; }; map1 { trip = <&target>; cooling-device = <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <1024>; }; map2 { trip = <&target>; cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <4096>; }; }; }; @@ -766,7 +830,7 @@ tsadc: tsadc@ff260000 { compatible = "rockchip,rk3399-tsadc"; reg = <0x0 0xff260000 0x0 0x100>; - interrupts = ; + interrupts = ; rockchip,grf = <&grf>; clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; clock-names = "tsadc", "apb_pclk"; @@ -783,136 +847,282 @@ status = "disabled"; }; - qos_gpu: qos_gpu@0xffae0000 { - compatible ="syscon"; - reg = <0x0 0xffae0000 0x0 0x20>; + qos_emmc: qos@ffa58000 { + compatible = "syscon"; + reg = <0x0 0xffa58000 0x0 0x20>; }; - qos_video_m0: qos_video_m0@0xffab8000 { - compatible ="syscon"; - reg = <0x0 0xffab8000 0x0 0x20>; + + qos_gmac: qos@ffa5c000 { + compatible = "syscon"; + reg = <0x0 0xffa5c000 0x0 0x20>; }; - qos_video_m1_r: qos_video_m1_r@0xffac0000 { - compatible ="syscon"; - reg = <0x0 0xffac0000 0x0 0x20>; + + qos_pcie: qos@ffa60080 { + compatible = "syscon"; + reg = <0x0 0xffa60080 0x0 0x20>; }; - qos_video_m1_w: qos_video_m1_w@0xffac0080 { - compatible ="syscon"; - reg = <0x0 0xffac0080 0x0 0x20>; + + qos_usb_host0: qos@ffa60100 { + compatible = "syscon"; + reg = <0x0 0xffa60100 0x0 0x20>; }; - qos_rga_r: qos_rga_r@0xffab0000 { - compatible ="syscon"; - reg = <0x0 0xffab0000 0x0 0x20>; + + qos_usb_host1: qos@ffa60180 { + compatible = "syscon"; + reg = <0x0 0xffa60180 0x0 0x20>; }; - qos_rga_w: qos_rga_w@0xffab0080 { - compatible ="syscon"; - reg = <0x0 0xffab0000 0x0 0x20>; + + qos_usb_otg0: qos@ffa70000 { + compatible = "syscon"; + reg = <0x0 0xffa70000 0x0 0x20>; }; - qos_iep: qos_iep@0xffa98000 { - compatible ="syscon"; - reg = <0x0 0xffa98000 0x0 0x20>; + + qos_usb_otg1: qos@ffa70080 { + compatible = "syscon"; + reg = <0x0 0xffa70080 0x0 0x20>; }; - qos_vop_big_r: qos_vop_big_r@0xffac8000 { - compatible ="syscon"; - reg = <0x0 0xffac8000 0x0 0x20>; + + qos_sd: qos@ffa74000 { + compatible = "syscon"; + reg = <0x0 0xffa74000 0x0 0x20>; }; - qos_vop_big_w: qos_vop_big_w@0xffac8080 { - compatible ="syscon"; - reg = <0x0 0xffac8080 0x0 0x20>; + + qos_sdioaudio: qos@ffa76000 { + compatible = "syscon"; + reg = <0x0 0xffa76000 0x0 0x20>; }; - qos_vop_little: qos_vop_little@0xffad0000 { - compatible ="syscon"; - reg = <0x0 0xffad0000 0x0 0x20>; + + qos_hdcp: qos@ffa90000 { + compatible = "syscon"; + reg = <0x0 0xffa90000 0x0 0x20>; }; - qos_isp0_m0: qos_isp0_m0@0xffaa0000 { - compatible ="syscon"; + + qos_iep: qos@ffa98000 { + compatible = "syscon"; + reg = <0x0 0xffa98000 0x0 0x20>; + }; + + qos_isp0_m0: qos@ffaa0000 { + compatible = "syscon"; reg = <0x0 0xffaa0000 0x0 0x20>; }; - qos_isp0_m1: qos_isp0_m1@0xffaa0080 { - compatible ="syscon"; + + qos_isp0_m1: qos@ffaa0080 { + compatible = "syscon"; reg = <0x0 0xffaa0080 0x0 0x20>; }; - qos_isp1_m0: qos_isp1_m0@0xffaa8000 { - compatible ="syscon"; + + qos_isp1_m0: qos@ffaa8000 { + compatible = "syscon"; reg = <0x0 0xffaa8000 0x0 0x20>; }; - qos_isp1_m1: qos_isp1_m1@0xffaa8080 { - compatible ="syscon"; + + qos_isp1_m1: qos@ffaa8080 { + compatible = "syscon"; reg = <0x0 0xffaa8080 0x0 0x20>; }; - qos_hdcp: qos_hdcp@0xffa90000 { - compatible ="syscon"; - reg = <0x0 0xffa90000 0x0 0x20>; + + qos_rga_r: qos@ffab0000 { + compatible = "syscon"; + reg = <0x0 0xffab0000 0x0 0x20>; + }; + + qos_rga_w: qos@ffab0080 { + compatible = "syscon"; + reg = <0x0 0xffab0080 0x0 0x20>; + }; + + qos_video_m0: qos@ffab8000 { + compatible = "syscon"; + reg = <0x0 0xffab8000 0x0 0x20>; + }; + + qos_video_m1_r: qos@ffac0000 { + compatible = "syscon"; + reg = <0x0 0xffac0000 0x0 0x20>; + }; + + qos_video_m1_w: qos@ffac0080 { + compatible = "syscon"; + reg = <0x0 0xffac0080 0x0 0x20>; + }; + + qos_vop_big_r: qos@ffac8000 { + compatible = "syscon"; + reg = <0x0 0xffac8000 0x0 0x20>; + }; + + qos_vop_big_w: qos@ffac8080 { + compatible = "syscon"; + reg = <0x0 0xffac8080 0x0 0x20>; + }; + + qos_vop_little: qos@ffad0000 { + compatible = "syscon"; + reg = <0x0 0xffad0000 0x0 0x20>; + }; + + qos_perihp: qos@ffad8080 { + compatible = "syscon"; + reg = <0x0 0xffad8080 0x0 0x20>; + }; + + qos_gpu: qos@ffae0000 { + compatible = "syscon"; + reg = <0x0 0xffae0000 0x0 0x20>; }; pmu: power-management@ff310000 { compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd"; reg = <0x0 0xff310000 0x0 0x1000>; + /* + * Note: RK3399 supports 6 voltage domains including VD_CORE_L, + * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU. + * Some of the power domains are grouped together for every + * voltage domain. + * The detail contents as below. + */ power: power-controller { - status = "okay"; compatible = "rockchip,rk3399-power-controller"; #power-domain-cells = <1>; #address-cells = <1>; #size-cells = <0>; - - pd_vdu { - reg = ; - pm_qos = <&qos_video_m1_r>, - <&qos_video_m1_w>; - }; - pd_vcodec { - reg = ; - pm_qos = <&qos_video_m0>; - }; - pd_iep { + /* These power domains are grouped by VD_CENTER */ + pd_iep@RK3399_PD_IEP { reg = ; + clocks = <&cru ACLK_IEP>, + <&cru HCLK_IEP>; pm_qos = <&qos_iep>; }; - pd_rga { + pd_rga@RK3399_PD_RGA { reg = ; + clocks = <&cru ACLK_RGA>, + <&cru HCLK_RGA>; pm_qos = <&qos_rga_r>, <&qos_rga_w>; }; - pd_vio { + pd_vcodec@RK3399_PD_VCODEC { + reg = ; + clocks = <&cru ACLK_VCODEC>, + <&cru HCLK_VCODEC>; + pm_qos = <&qos_video_m0>; + }; + pd_vdu@RK3399_PD_VDU { + reg = ; + clocks = <&cru ACLK_VDU>, + <&cru HCLK_VDU>; + pm_qos = <&qos_video_m1_r>, + <&qos_video_m1_w>; + }; + + /* These power domains are grouped by VD_GPU */ + pd_gpu@RK3399_PD_GPU { + reg = ; + clocks = <&cru ACLK_GPU>; + pm_qos = <&qos_gpu>; + }; + + /* These power domains are grouped by VD_LOGIC */ + pd_edp@RK3399_PD_EDP { + reg = ; + clocks = <&cru PCLK_EDP_CTRL>; + }; + pd_emmc@RK3399_PD_EMMC { + reg = ; + clocks = <&cru ACLK_EMMC>; + pm_qos = <&qos_emmc>; + }; + pd_gmac@RK3399_PD_GMAC { + reg = ; + clocks = <&cru ACLK_GMAC>; + pm_qos = <&qos_gmac>; + }; + pd_perihp@RK3399_PD_PERIHP { + reg = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru ACLK_PERIHP>; + pm_qos = <&qos_perihp>, + <&qos_pcie>, + <&qos_usb_host0>, + <&qos_usb_host1>; + + pd_sd@RK3399_PD_SD { + reg = ; + clocks = <&cru HCLK_SDMMC>, + <&cru SCLK_SDMMC>; + pm_qos = <&qos_sd>; + }; + }; + pd_sdioaudio@RK3399_PD_SDIOAUDIO { + reg = ; + clocks = <&cru HCLK_SDIO>; + pm_qos = <&qos_sdioaudio>; + }; + pd_usb3@RK3399_PD_USB3 { + reg = ; + clocks = <&cru ACLK_USB3>; + pm_qos = <&qos_usb_otg0>, + <&qos_usb_otg1>; + }; + pd_vio@RK3399_PD_VIO { reg = ; #address-cells = <1>; #size-cells = <0>; - pd_isp0 { + pd_hdcp@RK3399_PD_HDCP { + reg = ; + clocks = <&cru ACLK_HDCP>, + <&cru HCLK_HDCP>, + <&cru PCLK_HDCP>; + pm_qos = <&qos_hdcp>; + }; + pd_isp0@RK3399_PD_ISP0 { reg = ; + clocks = <&cru ACLK_ISP0>, + <&cru HCLK_ISP0>; pm_qos = <&qos_isp0_m0>, <&qos_isp0_m1>; }; - pd_isp1 { + pd_isp1@RK3399_PD_ISP1 { reg = ; + clocks = <&cru ACLK_ISP1>, + <&cru HCLK_ISP1>; pm_qos = <&qos_isp1_m0>, <&qos_isp1_m1>; }; - pd_hdcp { - reg = ; - pm_qos = <&qos_hdcp>; + pd_tcpc0@RK3399_PD_TCPC0 { + reg = ; + clocks = <&cru SCLK_UPHY0_TCPDCORE>, + <&cru SCLK_UPHY0_TCPDPHY_REF>; }; - pd_vo { + pd_tcpc1@RK3399_PD_TCPC1 { + reg = ; + clocks = <&cru SCLK_UPHY1_TCPDCORE>, + <&cru SCLK_UPHY1_TCPDPHY_REF>; + }; + pd_vo@RK3399_PD_VO { reg = ; #address-cells = <1>; #size-cells = <0>; - pd_vopb { + pd_vopb@RK3399_PD_VOPB { reg = ; + clocks = <&cru ACLK_VOP0>, + <&cru HCLK_VOP0>; pm_qos = <&qos_vop_big_r>, <&qos_vop_big_w>; }; - pd_vopl { + pd_vopl@RK3399_PD_VOPL { reg = ; + clocks = <&cru ACLK_VOP1>, + <&cru HCLK_VOP1>; pm_qos = <&qos_vop_little>; }; }; }; - pd_gpu { - reg = ; - pm_qos = <&qos_gpu>; - }; }; }; @@ -923,10 +1133,20 @@ reboot-mode { compatible = "syscon-reboot-mode"; offset = <0x300>; + mode-bootloader = ; + mode-charge = ; + mode-fastboot = ; + mode-loader = ; mode-normal = ; mode-recovery = ; - mode-bootloader = ; - mode-loader = ; + mode-ums = ; + }; + + pmu_pvtm: pmu-pvtm { + compatible = "rockchip,rk3399-pmu-pvtm"; + clocks = <&pmucru SCLK_PVTM_PMU>; + clock-names = "pmu"; + status = "disabled"; }; }; @@ -935,7 +1155,7 @@ reg = <0x0 0xff350000 0x0 0x1000>; clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>; clock-names = "spiclk", "apb_pclk"; - interrupts = ; + interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>; #address-cells = <1>; @@ -948,7 +1168,7 @@ reg = <0x0 0xff370000 0x0 0x100>; clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>; clock-names = "baudclk", "apb_pclk"; - interrupts = ; + interrupts = ; reg-shift = <2>; reg-io-width = <4>; pinctrl-names = "default"; @@ -961,7 +1181,7 @@ reg = <0x0 0xff3d0000 0x0 0x1000>; clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>; clock-names = "i2c", "pclk"; - interrupts = ; + interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&i2c4_xfer>; #address-cells = <1>; @@ -974,7 +1194,7 @@ reg = <0x0 0xff3e0000 0x0 0x1000>; clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>; clock-names = "i2c", "pclk"; - interrupts = ; + interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&i2c8_xfer>; #address-cells = <1>; @@ -982,42 +1202,52 @@ status = "disabled"; }; + pcie_phy: phy@e220 { + compatible = "rockchip,rk3399-pcie-phy"; + #phy-cells = <0>; + rockchip,grf = <&grf>; + clocks = <&cru SCLK_PCIEPHY_REF>; + clock-names = "refclk"; + resets = <&cru SRST_PCIEPHY>; + reset-names = "phy"; + status = "disabled"; + }; + pcie0: pcie@f8000000 { compatible = "rockchip,rk3399-pcie"; #address-cells = <3>; #size-cells = <2>; clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>, - <&cru PCLK_PCIE>, <&cru SCLK_PCIEPHY_REF>; - clock-names = "aclk_pcie", "aclk_perf_pcie", - "hclk_pcie", "clk_pciephy_ref"; + <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>; + clock-names = "aclk", "aclk-perf", + "hclk", "pm"; bus-range = <0x0 0x1>; - interrupts = , - , - ; - interrupt-names = "pcie-sys", "pcie-legacy", "pcie-client"; - ranges = < 0x82000000 0 0xfa000000 0x0 0xfa000000 0 0x600000 - 0x81000000 0 0xfa600000 0x0 0xfa600000 0 0x100000 >; - reg = < 0x0 0xf8000000 0x0 0x2000000 >, - < 0x0 0xfd000000 0x0 0x1000000 >; - reg-name = "axi-base", "apb-base"; - resets = <&cru SRST_PCIEPHY>, <&cru SRST_PCIE_CORE>, - <&cru SRST_PCIE_MGMT>, <&cru SRST_PCIE_MGMT_STICKY>, - <&cru SRST_PCIE_PIPE>; - reset-names = "phy-rst", "core-rst", "mgmt-rst", - "mgmt-sticky-rst", "pipe-rst"; - rockchip,grf = <&grf>; - pcie-conf = <0xe220>; - pcie-status = <0xe2a4>; - pcie-laneoff = <0xe214>; - msi-parent = <&its>; + msi-map = <0x0 &its 0x0 0x1000>; + interrupts = , + , + ; + interrupt-names = "sys", "legacy", "client"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie0 1>, - <0 0 0 2 &pcie0 2>, - <0 0 0 3 &pcie0 3>, - <0 0 0 4 &pcie0 4>; + interrupt-map = <0 0 0 1 &pcie0_intc 0>, + <0 0 0 2 &pcie0_intc 1>, + <0 0 0 3 &pcie0_intc 2>, + <0 0 0 4 &pcie0_intc 3>; + phys = <&pcie_phy>; + phy-names = "pcie-phy"; + ranges = <0x82000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000 + 0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>; + reg = <0x0 0xf8000000 0x0 0x2000000>, + <0x0 0xfd000000 0x0 0x1000000>; + reg-names = "axi-base", "apb-base"; + resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>, + <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>, + <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, + <&cru SRST_A_PCIE>; + reset-names = "core", "mgmt", "mgmt-sticky", "pipe", + "pm", "pclk", "aclk"; status = "disabled"; - pcie_intc: interrupt-controller { + pcie0_intc: interrupt-controller { interrupt-controller; #address-cells = <0>; #interrupt-cells = <1>; @@ -1068,18 +1298,77 @@ status = "disabled"; }; + dfi: dfi@ff630000 { + reg = <0x00 0xff630000 0x00 0x4000>; + compatible = "rockchip,rk3399-dfi"; + rockchip,pmu = <&pmugrf>; + clocks = <&cru PCLK_DDR_MON>; + clock-names = "pclk_ddr_mon"; + status = "disabled"; + }; + + dmc: dmc { + compatible = "rockchip,rk3399-dmc"; + devfreq-events = <&dfi>; + interrupts = ; + clocks = <&cru SCLK_DDRCLK>; + clock-names = "dmc_clk"; + ddr_timing = <&ddr_timing>; + operating-points-v2 = <&dmc_opp_table>; + status = "disabled"; + }; + + dmc_opp_table: dmc_opp_table { + compatible = "operating-points-v2"; + + opp00 { + opp-hz = /bits/ 64 <666000000>; + opp-microvolt = <900000>; + }; + }; + rga: rga@ff680000 { compatible = "rockchip,rk3399-rga"; reg = <0x0 0xff680000 0x0 0x10000>; - interrupts = ; + interrupts = ; interrupt-names = "rga"; clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>; clock-names = "aclk", "hclk", "sclk"; resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>; reset-names = "core", "axi", "ahb"; + power-domains = <&power RK3399_PD_RGA>; status = "disabled"; }; + efuse0: efuse@ff690000 { + compatible = "rockchip,rk3399-efuse"; + reg = <0x0 0xff690000 0x0 0x80>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cru PCLK_EFUSE1024NS>; + clock-names = "pclk_efuse"; + + /* Data cells */ + cpul_leakage: cpul-leakage { + reg = <0x1a 0x1>; + }; + cpub_leakage: cpub-leakage { + reg = <0x17 0x1>; + }; + gpu_leakage: gpu-leakage { + reg = <0x18 0x1>; + }; + center_leakage: center-leakage { + reg = <0x19 0x1>; + }; + logic_leakage: logic-leakage { + reg = <0x1b 0x1>; + }; + wafer_info: wafer-info { + reg = <0x1c 0x1>; + }; + }; + pmucru: pmu-clock-controller@ff750000 { compatible = "rockchip,rk3399-pmucru"; reg = <0x0 0xff750000 0x0 0x1000>; @@ -1099,7 +1388,7 @@ <&cru ACLK_VOP1>, <&cru HCLK_VOP1>, <&cru ARMCLKL>, <&cru ARMCLKB>, <&cru PLL_GPLL>, <&cru PLL_CPLL>, - <&cru PLL_NPLL>, + <&cru ACLK_GPU>, <&cru PLL_NPLL>, <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>, <&cru PCLK_PERIHP>, <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, @@ -1110,7 +1399,7 @@ <400000000>, <200000000>, <816000000>, <816000000>, <594000000>, <800000000>, - <1000000000>, + <200000000>, <1000000000>, <150000000>, <75000000>, <37500000>, <100000000>, <100000000>, @@ -1119,21 +1408,162 @@ }; grf: syscon@ff770000 { - compatible = "rockchip,rk3399-grf", "syscon"; + compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; reg = <0x0 0xff770000 0x0 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + + emmc_phy: phy@f780 { + compatible = "rockchip,rk3399-emmc-phy"; + reg = <0xf780 0x24>; + clocks = <&sdhci>; + clock-names = "emmcclk"; + #phy-cells = <0>; + status = "disabled"; + }; + + u2phy0: usb2-phy@e450 { + compatible = "rockchip,rk3399-usb2phy"; + reg = <0xe450 0x10>; + clocks = <&cru SCLK_USB2PHY0_REF>; + clock-names = "phyclk"; + #clock-cells = <0>; + clock-output-names = "clk_usbphy0_480m"; + status = "disabled"; + + u2phy0_otg: otg-port { + #phy-cells = <0>; + interrupts = , + , + ; + interrupt-names = "otg-bvalid", "otg-id", + "linestate"; + status = "disabled"; + }; + + u2phy0_host: host-port { + #phy-cells = <0>; + interrupts = ; + interrupt-names = "linestate"; + status = "disabled"; + }; + }; + + u2phy1: usb2-phy@e460 { + compatible = "rockchip,rk3399-usb2phy"; + reg = <0xe460 0x10>; + clocks = <&cru SCLK_USB2PHY1_REF>; + clock-names = "phyclk"; + #clock-cells = <0>; + clock-output-names = "clk_usbphy1_480m"; + status = "disabled"; + + u2phy1_otg: otg-port { + #phy-cells = <0>; + interrupts = , + , + ; + interrupt-names = "otg-bvalid", "otg-id", + "linestate"; + status = "disabled"; + }; + + u2phy1_host: host-port { + #phy-cells = <0>; + interrupts = ; + interrupt-names = "linestate"; + status = "disabled"; + }; + }; + + pvtm: pvtm { + compatible = "rockchip,rk3399-pvtm"; + clocks = <&cru SCLK_PVTM_CORE_L>, + <&cru SCLK_PVTM_CORE_B>, + <&cru SCLK_PVTM_GPU>, + <&cru SCLK_PVTM_DDR>; + clock-names = "core_l", "core_b", "gpu", "ddr"; + status = "disabled"; + }; }; - watchdog@ff840000 { + tcphy0: phy@ff7c0000 { + compatible = "rockchip,rk3399-typec-phy"; + reg = <0x0 0xff7c0000 0x0 0x40000>; + rockchip,grf = <&grf>; + #phy-cells = <1>; + clocks = <&cru SCLK_UPHY0_TCPDCORE>, + <&cru SCLK_UPHY0_TCPDPHY_REF>; + clock-names = "tcpdcore", "tcpdphy-ref"; + assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>; + assigned-clock-rates = <50000000>; + power-domains = <&power RK3399_PD_TCPD0>; + resets = <&cru SRST_UPHY0>, + <&cru SRST_UPHY0_PIPE_L00>, + <&cru SRST_P_UPHY0_TCPHY>; + reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; + rockchip,typec-conn-dir = <0xe580 0 16>; + rockchip,usb3tousb2-en = <0xe580 3 19>; + rockchip,usb3-host-disable = <0x2434 0 16>; + rockchip,usb3-host-port = <0x2434 12 28>; + rockchip,external-psm = <0xe588 14 30>; + rockchip,pipe-status = <0xe5c0 0 0>; + rockchip,uphy-dp-sel = <0x6268 19 19>; + status = "disabled"; + + tcphy0_dp: dp-port { + #phy-cells = <0>; + }; + + tcphy0_usb3: usb3-port { + #phy-cells = <0>; + }; + }; + + tcphy1: phy@ff800000 { + compatible = "rockchip,rk3399-typec-phy"; + reg = <0x0 0xff800000 0x0 0x40000>; + rockchip,grf = <&grf>; + #phy-cells = <1>; + clocks = <&cru SCLK_UPHY1_TCPDCORE>, + <&cru SCLK_UPHY1_TCPDPHY_REF>; + clock-names = "tcpdcore", "tcpdphy-ref"; + assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>; + assigned-clock-rates = <50000000>; + power-domains = <&power RK3399_PD_TCPD1>; + resets = <&cru SRST_UPHY1>, + <&cru SRST_UPHY1_PIPE_L00>, + <&cru SRST_P_UPHY1_TCPHY>; + reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; + rockchip,typec-conn-dir = <0xe58c 0 16>; + rockchip,usb3tousb2-en = <0xe58c 3 19>; + rockchip,usb3-host-disable = <0x2444 0 16>; + rockchip,usb3-host-port = <0x2444 12 28>; + rockchip,external-psm = <0xe594 14 30>; + rockchip,pipe-status = <0xe5c0 16 16>; + rockchip,uphy-dp-sel = <0x6268 3 19>; + status = "disabled"; + + tcphy1_dp: dp-port { + #phy-cells = <0>; + }; + + tcphy1_usb3: usb3-port { + #phy-cells = <0>; + }; + }; + + watchdog@ff848000 { compatible = "snps,dw-wdt"; - reg = <0x0 0xff840000 0x0 0x100>; + reg = <0x0 0xff848000 0x0 0x100>; clocks = <&cru PCLK_WDT>; - interrupts = ; + interrupts = ; }; rktimer: rktimer@ff850000 { compatible = "rockchip,rk3399-timer"; reg = <0x0 0xff850000 0x0 0x1000>; - interrupts = ; + interrupts = ; clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>; clock-names = "pclk", "timer"; }; @@ -1141,13 +1571,14 @@ spdif: spdif@ff870000 { compatible = "rockchip,rk3399-spdif"; reg = <0x0 0xff870000 0x0 0x1000>; - interrupts = ; + interrupts = ; dmas = <&dmac_bus 7>; dma-names = "tx"; clock-names = "mclk", "hclk"; clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>; pinctrl-names = "default"; pinctrl-0 = <&spdif_bus>; + power-domains = <&power RK3399_PD_SDIOAUDIO>; status = "disabled"; }; @@ -1155,37 +1586,40 @@ compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; reg = <0x0 0xff880000 0x0 0x1000>; rockchip,grf = <&grf>; - interrupts = ; + interrupts = ; dmas = <&dmac_bus 0>, <&dmac_bus 1>; dma-names = "tx", "rx"; clock-names = "i2s_clk", "i2s_hclk"; clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>; pinctrl-names = "default"; pinctrl-0 = <&i2s0_8ch_bus>; + power-domains = <&power RK3399_PD_SDIOAUDIO>; status = "disabled"; }; i2s1: i2s@ff890000 { compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; reg = <0x0 0xff890000 0x0 0x1000>; - interrupts = ; + interrupts = ; dmas = <&dmac_bus 2>, <&dmac_bus 3>; dma-names = "tx", "rx"; clock-names = "i2s_clk", "i2s_hclk"; clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>; pinctrl-names = "default"; pinctrl-0 = <&i2s1_2ch_bus>; + power-domains = <&power RK3399_PD_SDIOAUDIO>; status = "disabled"; }; i2s2: i2s@ff8a0000 { compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; reg = <0x0 0xff8a0000 0x0 0x1000>; - interrupts = ; + interrupts = ; dmas = <&dmac_bus 4>, <&dmac_bus 5>; dma-names = "tx", "rx"; clock-names = "i2s_clk", "i2s_hclk"; clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>; + power-domains = <&power RK3399_PD_SDIOAUDIO>; status = "disabled"; }; @@ -1197,24 +1631,25 @@ reg = <0x0 0xff9a0000 0x0 0x10000>; - interrupts = , - , - ; + interrupts = , + , + ; interrupt-names = "GPU", "JOB", "MMU"; clocks = <&cru ACLK_GPU>; clock-names = "clk_mali"; #cooling-cells = <2>; /* min followed by max */ operating-points-v2 = <&gpu_opp_table>; - + power-domains = <&power RK3399_PD_GPU>; + power-off-delay-ms = <200>; status = "disabled"; - power_model { + gpu_power_model: power_model { compatible = "arm,mali-simple-power-model"; voltage = <900>; frequency = <500>; static-power = <300>; - dynamic-power = <1780>; + dynamic-power = <396>; ts = <32000 4700 (-80) 2>; thermal-zone = "gpu-thermal"; }; @@ -1224,15 +1659,15 @@ compatible = "operating-points-v2"; opp-shared; - opp00 { + opp@200000000 { opp-hz = /bits/ 64 <200000000>; opp-microvolt = <900000>; }; - opp01 { + opp@300000000 { opp-hz = /bits/ 64 <300000000>; opp-microvolt = <900000>; }; - opp02 { + opp@400000000 { opp-hz = /bits/ 64 <400000000>; opp-microvolt = <900000>; }; @@ -1242,11 +1677,12 @@ vopl: vop@ff8f0000 { compatible = "rockchip,rk3399-vop-lit"; reg = <0x0 0xff8f0000 0x0 0x3efc>; - interrupts = ; + interrupts = ; clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>; clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>; reset-names = "axi", "ahb", "dclk"; + power-domains = <&power RK3399_PD_VOPL>; iommus = <&vopl_mmu>; status = "disabled"; @@ -1263,13 +1699,29 @@ reg = <1>; remote-endpoint = <&edp_in_vopl>; }; + + vopl_out_hdmi: endpoint@2 { + reg = <2>; + remote-endpoint = <&hdmi_in_vopl>; + }; }; }; + vop1_pwm: voppwm@ff8f01a0 { + compatible = "rockchip,vop-pwm"; + reg = <0x0 0xff8f01a0 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&vop1_pwm_pin>; + clocks = <&cru SCLK_VOP1_PWM>; + clock-names = "pwm"; + status = "disabled"; + }; + vopl_mmu: iommu@ff8f3f00 { compatible = "rockchip,iommu"; reg = <0x0 0xff8f3f00 0x0 0x100>; - interrupts = ; + interrupts = ; interrupt-names = "vopl_mmu"; #iommu-cells = <0>; status = "disabled"; @@ -1278,11 +1730,12 @@ vopb: vop@ff900000 { compatible = "rockchip,rk3399-vop-big"; reg = <0x0 0xff900000 0x0 0x3efc>; - interrupts = ; + interrupts = ; clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>; reset-names = "axi", "ahb", "dclk"; + power-domains = <&power RK3399_PD_VOPB>; iommus = <&vopb_mmu>; status = "disabled"; @@ -1299,25 +1752,71 @@ reg = <1>; remote-endpoint = <&mipi_in_vopb>; }; + + vopb_out_hdmi: endpoint@2 { + reg = <2>; + remote-endpoint = <&hdmi_in_vopb>; + }; }; }; + vop0_pwm: voppwm@ff9001a0 { + compatible = "rockchip,vop-pwm"; + reg = <0x0 0xff9001a0 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&vop0_pwm_pin>; + clocks = <&cru SCLK_VOP0_PWM>; + clock-names = "pwm"; + status = "disabled"; + }; + vopb_mmu: iommu@ff903f00 { compatible = "rockchip,iommu"; reg = <0x0 0xff903f00 0x0 0x100>; - interrupts = ; + interrupts = ; interrupt-names = "vopb_mmu"; #iommu-cells = <0>; status = "disabled"; }; + hdmi: hdmi@ff940000 { + compatible = "rockchip,rk3399-dw-hdmi"; + reg = <0x0 0xff940000 0x0 0x20000>; + reg-io-width = <4>; + rockchip,grf = <&grf>; + power-domains = <&power RK3399_PD_HDCP>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_i2c_xfer>; + interrupts = ; + clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, <&cru SCLK_HDMI_SFR>, <&cru PCLK_EDP_CTRL>; + clock-names = "iahb", "isfr", "vpll", "grf"; + status = "disabled"; + + ports { + hdmi_in: port { + #address-cells = <1>; + #size-cells = <0>; + hdmi_in_vopb: endpoint@0 { + reg = <0>; + remote-endpoint = <&vopb_out_hdmi>; + }; + hdmi_in_vopl: endpoint@1 { + reg = <1>; + remote-endpoint = <&vopl_out_hdmi>; + }; + }; + }; + }; + mipi_dsi: mipi@ff960000 { compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"; reg = <0x0 0xff960000 0x0 0x8000>; - interrupts = ; + interrupts = ; clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>, <&cru SCLK_DPHY_TX0_CFG>; clock-names = "ref", "pclk", "phy_cfg"; + power-domains = <&power RK3399_PD_VIO>; rockchip,grf = <&grf>; #address-cells = <1>; #size-cells = <0>; @@ -1347,9 +1846,10 @@ edp: edp@ff970000 { compatible = "rockchip,rk3399-edp"; reg = <0x0 0xff970000 0x0 0x8000>; - interrupts = ; + interrupts = ; clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>; clock-names = "dp", "pclk"; + power-domains = <&power RK3399_PD_EDP>; resets = <&cru SRST_P_EDP_CTRL>; reset-names = "dp"; rockchip,grf = <&grf>; @@ -1397,7 +1897,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x0 0xff720000 0x0 0x100>; clocks = <&pmucru PCLK_GPIO0_PMU>; - interrupts = ; + interrupts = ; gpio-controller; #gpio-cells = <0x2>; @@ -1410,7 +1910,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x0 0xff730000 0x0 0x100>; clocks = <&pmucru PCLK_GPIO1_PMU>; - interrupts = ; + interrupts = ; gpio-controller; #gpio-cells = <0x2>; @@ -1423,7 +1923,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x0 0xff780000 0x0 0x100>; clocks = <&cru PCLK_GPIO2>; - interrupts = ; + interrupts = ; gpio-controller; #gpio-cells = <0x2>; @@ -1436,7 +1936,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x0 0xff788000 0x0 0x100>; clocks = <&cru PCLK_GPIO3>; - interrupts = ; + interrupts = ; gpio-controller; #gpio-cells = <0x2>; @@ -1449,7 +1949,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x0 0xff790000 0x0 0x100>; clocks = <&cru PCLK_GPIO4>; - interrupts = ; + interrupts = ; gpio-controller; #gpio-cells = <0x2>; @@ -1470,6 +1970,21 @@ bias-disable; }; + pcfg_pull_up_20ma: pcfg-pull-up-20ma { + bias-pull-up; + drive-strength = <20>; + }; + + pcfg_pull_none_20ma: pcfg-pull-none-20ma { + bias-disable; + drive-strength = <20>; + }; + + pcfg_pull_none_18ma: pcfg-pull-none-18ma { + bias-disable; + drive-strength = <18>; + }; + pcfg_pull_none_12ma: pcfg-pull-none-12ma { bias-disable; drive-strength = <12>; @@ -1500,6 +2015,18 @@ drive-strength = <13>; }; + pcfg_output_high: pcfg-output-high { + output-high; + }; + + pcfg_output_low: pcfg-output-low { + output-low; + }; + + pcfg_input: pcfg-input { + input-enable; + }; + emmc { emmc_pwr: emmc-pwr { rockchip,pins = @@ -1762,6 +2289,11 @@ rockchip,pins = <4 21 RK_FUNC_1 &pcfg_pull_none>; }; + + spdif_bus_1: spdif-bus-1 { + rockchip,pins = + <3 16 RK_FUNC_3 &pcfg_pull_none>; + }; }; spi0 {