X-Git-Url: http://plrg.eecs.uci.edu/git/?p=firefly-linux-kernel-4.4.55.git;a=blobdiff_plain;f=arch%2Farm64%2Fboot%2Fdts%2Frockchip%2Frk3399.dtsi;h=699a9c832e7fb93afde68da93a6b63d6e048c755;hp=06ccec3ff172b8793b4892bc6818cb1b2cc549fc;hb=3779e671ad59ac61dd8750856f606a94cf4c811b;hpb=016a5e229299c89c4e645f6eda54146a8676924c diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 06ccec3ff172..699a9c832e7f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -50,6 +50,7 @@ / { compatible = "rockchip,rk3399"; + interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; @@ -113,6 +114,7 @@ enable-method = "psci"; #cooling-cells = <2>; /* min followed by max */ clocks = <&cru ARMCLKL>; + cpu-idle-states = <&cpu_sleep>; operating-points-v2 = <&cluster0_opp>; }; @@ -122,6 +124,7 @@ reg = <0x0 0x1>; enable-method = "psci"; clocks = <&cru ARMCLKL>; + cpu-idle-states = <&cpu_sleep>; operating-points-v2 = <&cluster0_opp>; }; @@ -131,6 +134,7 @@ reg = <0x0 0x2>; enable-method = "psci"; clocks = <&cru ARMCLKL>; + cpu-idle-states = <&cpu_sleep>; operating-points-v2 = <&cluster0_opp>; }; @@ -140,6 +144,7 @@ reg = <0x0 0x3>; enable-method = "psci"; clocks = <&cru ARMCLKL>; + cpu-idle-states = <&cpu_sleep>; operating-points-v2 = <&cluster0_opp>; }; @@ -150,6 +155,7 @@ enable-method = "psci"; #cooling-cells = <2>; /* min followed by max */ clocks = <&cru ARMCLKB>; + cpu-idle-states = <&cpu_sleep>; operating-points-v2 = <&cluster1_opp>; }; @@ -159,8 +165,21 @@ reg = <0x0 0x101>; enable-method = "psci"; clocks = <&cru ARMCLKB>; + cpu-idle-states = <&cpu_sleep>; operating-points-v2 = <&cluster1_opp>; }; + + idle-states { + entry-method = "psci"; + cpu_sleep: cpu-sleep-0 { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <350>; + exit-latency-us = <600>; + min-residency-us = <1150>; + }; + }; }; cluster0_opp: opp_table0 { @@ -169,20 +188,28 @@ opp00 { opp-hz = /bits/ 64 <408000000>; - opp-microvolt = <1000000>; + opp-microvolt = <800000>; clock-latency-ns = <40000>; }; opp01 { opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <1000000>; + opp-microvolt = <800000>; }; opp02 { opp-hz = /bits/ 64 <816000000>; - opp-microvolt = <1000000>; + opp-microvolt = <800000>; }; opp03 { opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <1000000>; + opp-microvolt = <875000>; + }; + opp04 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <925000>; + }; + opp05 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <1025000>; }; }; @@ -192,24 +219,24 @@ opp00 { opp-hz = /bits/ 64 <408000000>; - opp-microvolt = <1000000>; + opp-microvolt = <800000>; clock-latency-ns = <40000>; }; opp01 { opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <1000000>; + opp-microvolt = <800000>; }; opp02 { opp-hz = /bits/ 64 <816000000>; - opp-microvolt = <1000000>; + opp-microvolt = <800000>; }; opp03 { opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <1000000>; + opp-microvolt = <850000>; }; opp04 { opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1000000>; + opp-microvolt = <925000>; }; }; @@ -221,20 +248,9 @@ ; }; - pmu_a53 { - compatible = "arm,cortex-a53-pmu"; - interrupts = ; - interrupt-affinity = <&cpu_l0>, - <&cpu_l1>, - <&cpu_l2>, - <&cpu_l3>; - }; - - pmu_a72 { - compatible = "arm,cortex-a72-pmu", "arm,cortex-a57-pmu"; + arm-pmu { + compatible = "arm,armv8-pmuv3"; interrupts = ; - interrupt-affinity = <&cpu_b0>, - <&cpu_b1>; }; xin24m: xin24m { @@ -295,11 +311,13 @@ reg-offset = <0xf780>; #phy-cells = <0>; rockchip,grf = <&grf>; + ctrl-base = <0xfe330000>; status = "disabled"; }; sdio0: dwmmc@fe310000 { - compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc"; + compatible = "rockchip,rk3399-dw-mshc", + "rockchip,rk3288-dw-mshc"; reg = <0x0 0xfe310000 0x0 0x4000>; interrupts = ; clock-freq-min-max = <400000 150000000>; @@ -311,7 +329,8 @@ }; sdmmc: dwmmc@fe320000 { - compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc"; + compatible = "rockchip,rk3399-dw-mshc", + "rockchip,rk3288-dw-mshc"; reg = <0x0 0xfe320000 0x0 0x4000>; interrupts = ; clock-freq-min-max = <400000 150000000>; @@ -323,22 +342,46 @@ }; sdhci: sdhci@fe330000 { - compatible = "arasan,sdhci-5.1"; + compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1"; reg = <0x0 0xfe330000 0x0 0x10000>; interrupts = ; clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>; clock-names = "clk_xin", "clk_ahb"; + assigned-clocks = <&cru SCLK_EMMC>; + assigned-clock-parents = <&cru PLL_CPLL>; + assigned-clock-rates = <200000000>; phys = <&emmc_phy>; phy-names = "phy_arasan"; status = "disabled"; }; - usb_host0_echi: usb@fe380000 { + usb2phy: usb2phy { + compatible = "rockchip,rk3399-usb-phy"; + rockchip,grf = <&grf>; + #address-cells = <1>; + #size-cells = <0>; + + usb2phy0: usb2-phy0 { + #phy-cells = <0>; + #clock-cells = <0>; + reg = <0xe458>; + }; + + usb2phy1: usb2-phy1 { + #phy-cells = <0>; + #clock-cells = <0>; + reg = <0xe468>; + }; + }; + + usb_host0_ehci: usb@fe380000 { compatible = "generic-ehci"; reg = <0x0 0xfe380000 0x0 0x20000>; interrupts = ; - clocks = <&cru HCLK_HOST0>; - clock-names = "hclk_host0"; + clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>; + clock-names = "hclk_host0", "hclk_host0_arb"; + phys = <&usb2phy0>; + phy-names = "usb2_phy0"; status = "disabled"; }; @@ -346,17 +389,19 @@ compatible = "generic-ohci"; reg = <0x0 0xfe3a0000 0x0 0x20000>; interrupts = ; - clocks = <&cru HCLK_HOST0>; - clock-names = "hclk_host0"; + clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>; + clock-names = "hclk_host0", "hclk_host0_arb"; status = "disabled"; }; - usb_host1_echi: usb@fe3c0000 { + usb_host1_ehci: usb@fe3c0000 { compatible = "generic-ehci"; reg = <0x0 0xfe3c0000 0x0 0x20000>; interrupts = ; - clocks = <&cru HCLK_HOST1>; - clock-names = "hclk_host1"; + clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>; + clock-names = "hclk_host1", "hclk_host1_arb"; + phys = <&usb2phy1>; + phy-names = "usb2_phy1"; status = "disabled"; }; @@ -364,9 +409,63 @@ compatible = "generic-ohci"; reg = <0x0 0xfe3e0000 0x0 0x20000>; interrupts = ; - clocks = <&cru HCLK_HOST1>; - clock-names = "hclk_host1"; + clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>; + clock-names = "hclk_host1", "hclk_host1_arb"; + status = "disabled"; + }; + + usbdrd3_0: usb@fe800000 { + compatible = "rockchip,dwc3"; + clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>, + <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>, + <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>; + clock-names = "clk_usb3otg0_ref", "clk_usb3otg0_suspend", + "aclk_usb3otg0", "aclk_usb3_rksoc_axi_perf", + "aclk_usb3", "aclk_usb3_grf"; + #address-cells = <2>; + #size-cells = <2>; + ranges; status = "disabled"; + usbdrd_dwc3_0: dwc3 { + compatible = "snps,dwc3"; + reg = <0x0 0xfe800000 0x0 0x100000>; + interrupts = ; + dr_mode = "otg"; + tx-fifo-resize; + snps,dis_enblslpm_quirk; + snps,phyif_utmi_16_bits; + snps,dis_u2_freeclk_exists_quirk; + snps,dis_del_phy_power_chg_quirk; + snps,xhci_slow_suspend_quirk; + status = "disabled"; + }; + }; + + usbdrd3_1: usb@fe900000 { + compatible = "rockchip,dwc3"; + clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>, + <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>, + <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>; + clock-names = "clk_usb3otg1_ref", "clk_usb3otg1_suspend", + "aclk_usb3otg1", "aclk_usb3_rksoc_axi_perf", + "aclk_usb3", "aclk_usb3_grf"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + usbdrd_dwc3_1: dwc3 { + compatible = "snps,dwc3"; + reg = <0x0 0xfe900000 0x0 0x100000>; + interrupts = ; + dr_mode = "otg"; + tx-fifo-resize; + snps,dis_enblslpm_quirk; + snps,phyif_utmi_16_bits; + snps,dis_u2_freeclk_exists_quirk; + snps,dis_del_phy_power_chg_quirk; + snps,xhci_slow_suspend_quirk; + status = "disabled"; + }; }; gic: interrupt-controller@fee00000 { @@ -499,8 +598,8 @@ interrupts = ; reg-shift = <2>; reg-io-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; status = "disabled"; }; @@ -512,8 +611,8 @@ interrupts = ; reg-shift = <2>; reg-io-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_xfer>; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_xfer>; status = "disabled"; }; @@ -525,8 +624,8 @@ interrupts = ; reg-shift = <2>; reg-io-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&uart2c_xfer>; + pinctrl-names = "default"; + pinctrl-0 = <&uart2c_xfer>; status = "disabled"; }; @@ -538,8 +637,8 @@ interrupts = ; reg-shift = <2>; reg-io-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>; + pinctrl-names = "default"; + pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>; status = "disabled"; }; @@ -609,15 +708,83 @@ }; thermal-zones { - #include "rk3368-thermal.dtsi" + cpu { + polling-delay-passive = <100>; /* milliseconds */ + polling-delay = <1000>; /* milliseconds */ + + thermal-sensors = <&tsadc 0>; + + trips { + cpu_alert0: cpu_alert0 { + temperature = <70000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + cpu_alert1: cpu_alert1 { + temperature = <75000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + cpu_crit: cpu_crit { + temperature = <95000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = + <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu_alert1>; + cooling-device = + <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + gpu { + polling-delay-passive = <100>; /* milliseconds */ + polling-delay = <1000>; /* milliseconds */ + + thermal-sensors = <&tsadc 1>; + + trips { + gpu_alert0: gpu_alert0 { + temperature = <75000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + gpu_crit: gpu_crit { + temperature = <95000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&gpu_alert0>; + cooling-device = + <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; }; tsadc: tsadc@ff260000 { compatible = "rockchip,rk3399-tsadc"; reg = <0x0 0xff260000 0x0 0x100>; interrupts = ; + rockchip,grf = <&grf>; clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; clock-names = "tsadc", "apb_pclk"; + assigned-clocks = <&cru SCLK_TSADC>; + assigned-clock-rates = <750000>; resets = <&cru SRST_TSADC>; reset-names = "tsadc-apb"; pinctrl-names = "init", "default", "sleep"; @@ -629,7 +796,68 @@ status = "disabled"; }; - pmu: power-management@ff31000 { + qos_gpu: qos_gpu@0xffae0000 { + compatible ="syscon"; + reg = <0x0 0xffae0000 0x0 0x20>; + }; + qos_video_m0: qos_video_m0@0xffab8000 { + compatible ="syscon"; + reg = <0x0 0xffab8000 0x0 0x20>; + }; + qos_video_m1_r: qos_video_m1_r@0xffac0000 { + compatible ="syscon"; + reg = <0x0 0xffac0000 0x0 0x20>; + }; + qos_video_m1_w: qos_video_m1_w@0xffac0080 { + compatible ="syscon"; + reg = <0x0 0xffac0080 0x0 0x20>; + }; + qos_rga_r: qos_rga_r@0xffab0000 { + compatible ="syscon"; + reg = <0x0 0xffab0000 0x0 0x20>; + }; + qos_rga_w: qos_rga_w@0xffab0080 { + compatible ="syscon"; + reg = <0x0 0xffab0000 0x0 0x20>; + }; + qos_iep: qos_iep@0xffa98000 { + compatible ="syscon"; + reg = <0x0 0xffa98000 0x0 0x20>; + }; + qos_vop_big_r: qos_vop_big_r@0xffac8000 { + compatible ="syscon"; + reg = <0x0 0xffac8000 0x0 0x20>; + }; + qos_vop_big_w: qos_vop_big_w@0xffac8080 { + compatible ="syscon"; + reg = <0x0 0xffac8080 0x0 0x20>; + }; + qos_vop_little: qos_vop_little@0xffad0000 { + compatible ="syscon"; + reg = <0x0 0xffad0000 0x0 0x20>; + }; + qos_isp0_m0: qos_isp0_m0@0xffaa0000 { + compatible ="syscon"; + reg = <0x0 0xffaa0000 0x0 0x20>; + }; + qos_isp0_m1: qos_isp0_m1@0xffaa0080 { + compatible ="syscon"; + reg = <0x0 0xffaa0080 0x0 0x20>; + }; + qos_isp1_m0: qos_isp1_m0@0xffaa8000 { + compatible ="syscon"; + reg = <0x0 0xffaa8000 0x0 0x20>; + }; + qos_isp1_m1: qos_isp1_m1@0xffaa8080 { + compatible ="syscon"; + reg = <0x0 0xffaa8080 0x0 0x20>; + }; + qos_hdcp: qos_hdcp@0xffa90000 { + compatible ="syscon"; + reg = <0x0 0xffa90000 0x0 0x20>; + }; + + pmu: power-management@ff310000 { compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd"; reg = <0x0 0xff310000 0x0 0x1000>; @@ -647,15 +875,21 @@ pd_vdu { reg = ; + pm_qos = <&qos_video_m1_r>, + <&qos_video_m1_w>; }; pd_vcodec { reg = ; + pm_qos = <&qos_video_m0>; }; pd_iep { reg = ; + pm_qos = <&qos_iep>; }; pd_rga { reg = ; + pm_qos = <&qos_rga_r>, + <&qos_rga_w>; }; }; pd_vio { @@ -665,12 +899,17 @@ pd_isp0 { reg = ; + pm_qos = <&qos_isp0_m0>, + <&qos_isp0_m1>; }; pd_isp1 { reg = ; + pm_qos = <&qos_isp1_m0>, + <&qos_isp1_m1>; }; pd_hdcp { reg = ; + pm_qos = <&qos_hdcp>; }; pd_vo { reg = ; @@ -679,14 +918,18 @@ pd_vopb { reg = ; + pm_qos = <&qos_vop_big_r>, + <&qos_vop_big_w>; }; pd_vopl { reg = ; + pm_qos = <&qos_vop_little>; }; }; }; pd_gpu { reg = ; + pm_qos = <&qos_gpu>; }; }; }; @@ -748,6 +991,48 @@ status = "disabled"; }; + pcie0: pcie@f8000000 { + compatible = "rockchip,rk3399-pcie"; + #address-cells = <3>; + #size-cells = <2>; + clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>, + <&cru PCLK_PCIE>, <&cru SCLK_PCIEPHY_REF>; + clock-names = "aclk_pcie", "aclk_perf_pcie", + "hclk_pcie", "clk_pciephy_ref"; + bus-range = <0x0 0x1>; + interrupts = , + , + ; + interrupt-names = "pcie-sys", "pcie-legacy", "pcie-client"; + ranges = < 0x82000000 0 0xfa000000 0x0 0xfa000000 0 0x600000 + 0x81000000 0 0xfa600000 0x0 0xfa600000 0 0x100000 >; + reg = < 0x0 0xf8000000 0x0 0x2000000 >, + < 0x0 0xfd000000 0x0 0x1000000 >; + reg-name = "axi-base", "apb-base"; + resets = <&cru SRST_PCIEPHY>, <&cru SRST_PCIE_CORE>, + <&cru SRST_PCIE_MGMT>, <&cru SRST_PCIE_MGMT_STICKY>, + <&cru SRST_PCIE_PIPE>; + reset-names = "phy-rst", "core-rst", "mgmt-rst", + "mgmt-sticky-rst", "pipe-rst"; + rockchip,grf = <&grf>; + pcie-conf = <0xe220>; + pcie-status = <0xe2a4>; + pcie-laneoff = <0xe214>; + msi-parent = <&its>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie0 1>, + <0 0 0 2 &pcie0 2>, + <0 0 0 3 &pcie0 3>, + <0 0 0 4 &pcie0 4>; + status = "disabled"; + pcie_intc: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + pwm0: pwm@ff420000 { compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; reg = <0x0 0xff420000 0x0 0x10>; @@ -792,10 +1077,21 @@ status = "disabled"; }; + rga: rga@ff680000 { + compatible = "rockchip,rk3399-rga"; + reg = <0x0 0xff680000 0x0 0x10000>; + interrupts = ; + interrupt-names = "rga"; + clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>; + clock-names = "aclk", "hclk", "sclk"; + resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>; + reset-names = "core", "axi", "ahb"; + status = "disabled"; + }; + pmucru: pmu-clock-controller@ff750000 { compatible = "rockchip,rk3399-pmucru"; reg = <0x0 0xff750000 0x0 0x1000>; - rockchip,grf = <&pmugrf>; #clock-cells = <1>; #reset-cells = <1>; assigned-clocks = <&pmucru PLL_PPLL>; @@ -805,10 +1101,12 @@ cru: clock-controller@ff760000 { compatible = "rockchip,rk3399-cru"; reg = <0x0 0xff760000 0x0 0x1000>; - rockchip,grf = <&grf>; #clock-cells = <1>; #reset-cells = <1>; assigned-clocks = + <&cru ACLK_VOP0>, <&cru HCLK_VOP0>, + <&cru ACLK_VOP1>, <&cru HCLK_VOP1>, + <&cru ARMCLKL>, <&cru ARMCLKB>, <&cru PLL_GPLL>, <&cru PLL_CPLL>, <&cru PLL_NPLL>, <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>, @@ -817,6 +1115,9 @@ <&cru PCLK_PERILP0>, <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>; assigned-clock-rates = + <400000000>, <200000000>, + <400000000>, <200000000>, + <816000000>, <1008000000>, <594000000>, <800000000>, <1000000000>, <150000000>, <75000000>, @@ -831,12 +1132,19 @@ reg = <0x0 0xff770000 0x0 0x10000>; }; - wdt0: watchdog@ff840000 { + watchdog@ff840000 { compatible = "snps,dw-wdt"; reg = <0x0 0xff840000 0x0 0x100>; clocks = <&cru PCLK_WDT>; interrupts = ; - status = "disabled"; + }; + + rktimer: rktimer@ff850000 { + compatible = "rockchip,rk3399-timer"; + reg = <0x0 0xff850000 0x0 0x1000>; + interrupts = ; + clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>; + clock-names = "pclk", "timer"; }; spdif: spdif@ff870000 { @@ -845,8 +1153,8 @@ interrupts = ; dmas = <&dmac_bus 7>; dma-names = "tx"; - clock-names = "hclk", "mclk"; - clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF_8CH>; + clock-names = "mclk", "hclk"; + clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>; pinctrl-names = "default"; pinctrl-0 = <&spdif_bus>; status = "disabled"; @@ -855,13 +1163,12 @@ i2s0: i2s@ff880000 { compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; reg = <0x0 0xff880000 0x0 0x1000>; + rockchip,grf = <&grf>; interrupts = ; - #address-cells = <1>; - #size-cells = <0>; dmas = <&dmac_bus 0>, <&dmac_bus 1>; dma-names = "tx", "rx"; - clock-names = "i2s_hclk", "i2s_clk"; - clocks = <&cru HCLK_I2S0_8CH>, <&cru SCLK_I2S0_8CH>; + clock-names = "i2s_clk", "i2s_hclk"; + clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>; pinctrl-names = "default"; pinctrl-0 = <&i2s0_8ch_bus>; status = "disabled"; @@ -871,12 +1178,10 @@ compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; reg = <0x0 0xff890000 0x0 0x1000>; interrupts = ; - #address-cells = <1>; - #size-cells = <0>; dmas = <&dmac_bus 2>, <&dmac_bus 3>; dma-names = "tx", "rx"; - clock-names = "i2s_hclk", "i2s_clk"; - clocks = <&cru HCLK_I2S1_8CH>, <&cru SCLK_I2S1_8CH>; + clock-names = "i2s_clk", "i2s_hclk"; + clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>; pinctrl-names = "default"; pinctrl-0 = <&i2s1_2ch_bus>; status = "disabled"; @@ -886,12 +1191,206 @@ compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; reg = <0x0 0xff8a0000 0x0 0x1000>; interrupts = ; - #address-cells = <1>; - #size-cells = <0>; dmas = <&dmac_bus 4>, <&dmac_bus 5>; dma-names = "tx", "rx"; - clock-names = "i2s_hclk", "i2s_clk"; - clocks = <&cru HCLK_I2S2_8CH>, <&cru SCLK_I2S2_8CH>; + clock-names = "i2s_clk", "i2s_hclk"; + clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>; + status = "disabled"; + }; + + gpu: gpu@ff9a0000 { + compatible = "arm,malit860", + "arm,malit86x", + "arm,malit8xx", + "arm,mali-midgard"; + + reg = <0x0 0xff9a0000 0x0 0x10000>; + + interrupts = , + , + ; + interrupt-names = "GPU", "JOB", "MMU"; + + clocks = <&cru ACLK_GPU>; + clock-names = "clk_mali"; + #cooling-cells = <2>; /* min followed by max */ + operating-points-v2 = <&gpu_opp_table>; + + status = "disabled"; + + power_model { + compatible = "arm,mali-simple-power-model"; + voltage = <900>; + frequency = <500>; + static-power = <500>; + dynamic-power = <1500>; + ts = <20000 2000 (-20) 2>; + thermal-zone = "gpu"; + }; + }; + + gpu_opp_table: gpu_opp_table { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <900000>; + }; + opp01 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <900000>; + }; + opp02 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <900000>; + }; + + }; + + vopl: vop@ff8f0000 { + compatible = "rockchip,rk3399-vop-lit"; + reg = <0x0 0xff8f0000 0x0 0x3efc>; + interrupts = ; + clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>; + clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; + resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>; + reset-names = "axi", "ahb", "dclk"; + iommus = <&vopl_mmu>; + status = "disabled"; + + vopl_out: port { + #address-cells = <1>; + #size-cells = <0>; + + vopl_out_mipi: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_in_vopl>; + }; + + vopl_out_edp: endpoint@1 { + reg = <1>; + remote-endpoint = <&edp_in_vopl>; + }; + }; + }; + + vopl_mmu: iommu@ff8f3f00 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff8f3f00 0x0 0x100>; + interrupts = ; + interrupt-names = "vopl_mmu"; + #iommu-cells = <0>; + status = "disabled"; + }; + + vopb: vop@ff900000 { + compatible = "rockchip,rk3399-vop-big"; + reg = <0x0 0xff900000 0x0 0x3efc>; + interrupts = ; + clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; + clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; + resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>; + reset-names = "axi", "ahb", "dclk"; + iommus = <&vopb_mmu>; + status = "disabled"; + + vopb_out: port { + #address-cells = <1>; + #size-cells = <0>; + + vopb_out_edp: endpoint@0 { + reg = <0>; + remote-endpoint = <&edp_in_vopb>; + }; + + vopb_out_mipi: endpoint@1 { + reg = <1>; + remote-endpoint = <&mipi_in_vopb>; + }; + }; + }; + + vopb_mmu: iommu@ff903f00 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff903f00 0x0 0x100>; + interrupts = ; + interrupt-names = "vopb_mmu"; + #iommu-cells = <0>; + status = "disabled"; + }; + + mipi_dsi: mipi@ff960000 { + compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"; + reg = <0x0 0xff960000 0x0 0x8000>; + interrupts = ; + clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>, + <&cru SCLK_DPHY_TX0_CFG>; + clock-names = "ref", "pclk", "phy_cfg"; + rockchip,grf = <&grf>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + mipi_in: port { + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_vopb: endpoint@0 { + reg = <0>; + remote-endpoint = <&vopb_out_mipi>; + }; + mipi_in_vopl: endpoint@1 { + reg = <1>; + remote-endpoint = <&vopl_out_mipi>; + }; + }; + }; + }; + + edp: edp@ff970000 { + compatible = "rockchip,rk3399-edp"; + reg = <0x0 0xff970000 0x0 0x8000>; + interrupts = ; + clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>; + clock-names = "dp", "pclk"; + resets = <&cru SRST_P_EDP_CTRL>; + reset-names = "dp"; + rockchip,grf = <&grf>; + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&edp_hpd>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + edp_in: port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + edp_in_vopb: endpoint@0 { + reg = <0>; + remote-endpoint = <&vopb_out_edp>; + }; + + edp_in_vopl: endpoint@1 { + reg = <1>; + remote-endpoint = <&vopl_out_edp>; + }; + }; + }; + }; + + display_subsystem: display-subsystem { + compatible = "rockchip,display-subsystem"; + ports = <&vopl_out>, <&vopb_out>; status = "disabled"; }; @@ -1005,6 +1504,11 @@ drive-strength = <12>; }; + pcfg_pull_none_13ma: pcfg-pull-none-13ma { + bias-disable; + drive-strength = <13>; + }; + emmc { emmc_pwr: emmc-pwr { rockchip,pins = @@ -1016,13 +1520,13 @@ rgmii_pins: rgmii-pins { rockchip,pins = /* mac_txclk */ - <3 17 RK_FUNC_1 &pcfg_pull_none_12ma>, + <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>, /* mac_rxclk */ <3 14 RK_FUNC_1 &pcfg_pull_none>, /* mac_mdio */ <3 13 RK_FUNC_1 &pcfg_pull_none>, /* mac_txen */ - <3 12 RK_FUNC_1 &pcfg_pull_none_12ma>, + <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>, /* mac_clk */ <3 11 RK_FUNC_1 &pcfg_pull_none>, /* mac_rxdv */ @@ -1034,17 +1538,17 @@ /* mac_rxd0 */ <3 6 RK_FUNC_1 &pcfg_pull_none>, /* mac_txd1 */ - <3 5 RK_FUNC_1 &pcfg_pull_none_12ma>, + <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>, /* mac_txd0 */ - <3 4 RK_FUNC_1 &pcfg_pull_none_12ma>, + <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>, /* mac_rxd3 */ <3 3 RK_FUNC_1 &pcfg_pull_none>, /* mac_rxd2 */ <3 2 RK_FUNC_1 &pcfg_pull_none>, /* mac_txd3 */ - <3 1 RK_FUNC_1 &pcfg_pull_none_12ma>, + <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>, /* mac_txd2 */ - <3 0 RK_FUNC_1 &pcfg_pull_none_12ma>; + <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>; }; rmii_pins: rmii-pins { @@ -1052,7 +1556,7 @@ /* mac_mdio */ <3 13 RK_FUNC_1 &pcfg_pull_none>, /* mac_txen */ - <3 12 RK_FUNC_1 &pcfg_pull_none_12ma>, + <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>, /* mac_clk */ <3 11 RK_FUNC_1 &pcfg_pull_none>, /* mac_rxer */ @@ -1066,9 +1570,9 @@ /* mac_rxd0 */ <3 6 RK_FUNC_1 &pcfg_pull_none>, /* mac_txd1 */ - <3 5 RK_FUNC_1 &pcfg_pull_none_12ma>, + <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>, /* mac_txd0 */ - <3 4 RK_FUNC_1 &pcfg_pull_none_12ma>; + <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>; }; }; @@ -1102,6 +1606,13 @@ <4 17 RK_FUNC_1 &pcfg_pull_none>, <4 16 RK_FUNC_1 &pcfg_pull_none>; }; + + i2c3_gpio: i2c3_gpio { + rockchip,pins = + <4 17 RK_FUNC_GPIO &pcfg_pull_none>, + <4 16 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; i2c4 { @@ -1519,10 +2030,35 @@ }; }; - pmic { - pmic_int_l: pmic-int-l { + edp { + edp_hpd: edp-hpd { + rockchip,pins = + <4 23 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + hdmi { + hdmi_i2c_xfer: hdmi-i2c-xfer { + rockchip,pins = + <4 17 RK_FUNC_3 &pcfg_pull_none>, + <4 16 RK_FUNC_3 &pcfg_pull_none>; + }; + + hdmi_cec: hdmi-cec { + rockchip,pins = + <4 23 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + pcie { + pcie_clkreqn: pci-clkreqn { + rockchip,pins = + <2 26 RK_FUNC_2 &pcfg_pull_none>; + }; + + pcie_clkreqnb: pci-clkreqnb { rockchip,pins = - <1 21 RK_FUNC_GPIO &pcfg_pull_up>; + <4 24 RK_FUNC_1 &pcfg_pull_none>; }; }; };