X-Git-Url: http://plrg.eecs.uci.edu/git/?p=firefly-linux-kernel-4.4.55.git;a=blobdiff_plain;f=arch%2Farm64%2Fboot%2Fdts%2Frockchip%2Frk3399.dtsi;h=3f792cf8f535223a623991d8df575356fabebf79;hp=1cc78265c3cbe5bcec126c8d247261a06482f482;hb=5cce639363fd3624ce31952119b6aba77db8c953;hpb=0f13a2d669fa9dc2fcb7b2c913edf3b8763eba50 diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 1cc78265c3cb..3f792cf8f535 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -46,10 +46,12 @@ #include #include #include +#include #include / { compatible = "rockchip,rk3399"; + interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; @@ -68,6 +70,12 @@ serial1 = &uart1; serial2 = &uart2; serial3 = &uart3; + serial4 = &uart4; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; }; cpus { @@ -104,75 +112,116 @@ device_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x0>; - + enable-method = "psci"; #cooling-cells = <2>; /* min followed by max */ + dynamic-power-coefficient = <100>; clocks = <&cru ARMCLKL>; + cpu-idle-states = <&cpu_sleep>; operating-points-v2 = <&cluster0_opp>; + sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>; }; cpu_l1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x1>; + enable-method = "psci"; clocks = <&cru ARMCLKL>; + cpu-idle-states = <&cpu_sleep>; operating-points-v2 = <&cluster0_opp>; + sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>; }; cpu_l2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x2>; + enable-method = "psci"; clocks = <&cru ARMCLKL>; + cpu-idle-states = <&cpu_sleep>; operating-points-v2 = <&cluster0_opp>; + sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>; }; cpu_l3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x3>; + enable-method = "psci"; clocks = <&cru ARMCLKL>; + cpu-idle-states = <&cpu_sleep>; operating-points-v2 = <&cluster0_opp>; + sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>; }; cpu_b0: cpu@100 { device_type = "cpu"; compatible = "arm,cortex-a72", "arm,armv8"; reg = <0x0 0x100>; - + enable-method = "psci"; #cooling-cells = <2>; /* min followed by max */ + dynamic-power-coefficient = <436>; clocks = <&cru ARMCLKB>; + cpu-idle-states = <&cpu_sleep>; operating-points-v2 = <&cluster1_opp>; + sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>; }; cpu_b1: cpu@101 { device_type = "cpu"; compatible = "arm,cortex-a72", "arm,armv8"; reg = <0x0 0x101>; + enable-method = "psci"; clocks = <&cru ARMCLKB>; + cpu-idle-states = <&cpu_sleep>; operating-points-v2 = <&cluster1_opp>; + sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>; }; + + idle-states { + entry-method = "psci"; + cpu_sleep: cpu-sleep-0 { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <350>; + exit-latency-us = <600>; + min-residency-us = <1150>; + }; + }; + + /include/ "rk3399-sched-energy.dtsi" + }; cluster0_opp: opp_table0 { compatible = "operating-points-v2"; opp-shared; - opp00 { + opp@408000000 { opp-hz = /bits/ 64 <408000000>; - opp-microvolt = <1000000>; + opp-microvolt = <800000>; clock-latency-ns = <40000>; }; - opp01 { + opp@600000000 { opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <1000000>; + opp-microvolt = <800000>; }; - opp02 { + opp@816000000 { opp-hz = /bits/ 64 <816000000>; - opp-microvolt = <1000000>; + opp-microvolt = <800000>; }; - opp03 { + opp@1008000000 { opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <1000000>; + opp-microvolt = <875000>; + }; + opp@1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <925000>; + }; + opp@1416000000 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <1025000>; }; }; @@ -180,35 +229,45 @@ compatible = "operating-points-v2"; opp-shared; - opp00 { + opp@408000000 { opp-hz = /bits/ 64 <408000000>; - opp-microvolt = <1000000>; + opp-microvolt = <800000>; clock-latency-ns = <40000>; }; - opp01 { + opp@600000000 { opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <1000000>; + opp-microvolt = <800000>; }; - opp02 { + opp@816000000 { opp-hz = /bits/ 64 <816000000>; - opp-microvolt = <1000000>; + opp-microvolt = <800000>; }; - opp03 { + opp@1008000000 { opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <1000000>; + opp-microvolt = <850000>; }; - opp04 { + opp@1200000000 { opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1000000>; + opp-microvolt = <925000>; }; }; timer { compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; + interrupts = , + , + , + ; + }; + + pmu_a53 { + compatible = "arm,cortex-a53-pmu"; + interrupts = ; + }; + + pmu_a72 { + compatible = "arm,cortex-a72-pmu"; + interrupts = ; }; xin24m: xin24m { @@ -227,106 +286,204 @@ dmac_bus: dma-controller@ff6d0000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x0 0xff6d0000 0x0 0x4000>; - interrupts = , - ; + interrupts = , + ; #dma-cells = <1>; clocks = <&cru ACLK_DMAC0_PERILP>; clock-names = "apb_pclk"; + peripherals-req-type-burst; }; dmac_peri: dma-controller@ff6e0000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x0 0xff6e0000 0x0 0x4000>; - interrupts = , - ; + interrupts = , + ; #dma-cells = <1>; clocks = <&cru ACLK_DMAC1_PERILP>; clock-names = "apb_pclk"; + peripherals-req-type-burst; }; }; + gmac: eth@fe300000 { + compatible = "rockchip,rk3399-gmac"; + reg = <0x0 0xfe300000 0x0 0x10000>; + rockchip,grf = <&grf>; + interrupts = ; + interrupt-names = "macirq"; + clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>, + <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>, + <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>, + <&cru PCLK_GMAC>; + clock-names = "stmmaceth", "mac_clk_rx", + "mac_clk_tx", "clk_mac_ref", + "clk_mac_refout", "aclk_mac", + "pclk_mac"; + resets = <&cru SRST_A_GMAC>; + reset-names = "stmmaceth"; + status = "disabled"; + }; + emmc_phy: phy { compatible = "rockchip,rk3399-emmc-phy"; reg-offset = <0xf780>; #phy-cells = <0>; rockchip,grf = <&grf>; + ctrl-base = <0xfe330000>; status = "disabled"; }; sdio0: dwmmc@fe310000 { - compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc"; + compatible = "rockchip,rk3399-dw-mshc", + "rockchip,rk3288-dw-mshc"; reg = <0x0 0xfe310000 0x0 0x4000>; - interrupts = ; + interrupts = ; clock-freq-min-max = <400000 150000000>; clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; fifo-depth = <0x100>; + power-domains = <&power RK3399_PD_SDIOAUDIO>; status = "disabled"; }; sdmmc: dwmmc@fe320000 { - compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc"; + compatible = "rockchip,rk3399-dw-mshc", + "rockchip,rk3288-dw-mshc"; reg = <0x0 0xfe320000 0x0 0x4000>; - interrupts = ; + interrupts = ; clock-freq-min-max = <400000 150000000>; clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; fifo-depth = <0x100>; + power-domains = <&power RK3399_PD_SD>; status = "disabled"; }; sdhci: sdhci@fe330000 { - compatible = "arasan,sdhci-5.1"; + compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1"; reg = <0x0 0xfe330000 0x0 0x10000>; - interrupts = ; + interrupts = ; clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>; clock-names = "clk_xin", "clk_ahb"; + assigned-clocks = <&cru SCLK_EMMC>; + assigned-clock-parents = <&cru PLL_CPLL>; + assigned-clock-rates = <200000000>; phys = <&emmc_phy>; phy-names = "phy_arasan"; + power-domains = <&power RK3399_PD_EMMC>; status = "disabled"; }; - usb_host0_echi: usb@fe380000 { + usb_host0_ehci: usb@fe380000 { compatible = "generic-ehci"; reg = <0x0 0xfe380000 0x0 0x20000>; - interrupts = ; - clocks = <&cru HCLK_HOST0>; - clock-names = "hclk_host0"; + interrupts = ; + clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, + <&cru SCLK_USBPHY0_480M_SRC>; + clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m"; + phys = <&u2phy0_host>; + phy-names = "usb"; status = "disabled"; }; usb_host0_ohci: usb@fe3a0000 { compatible = "generic-ohci"; reg = <0x0 0xfe3a0000 0x0 0x20000>; - interrupts = ; - clocks = <&cru HCLK_HOST0>; - clock-names = "hclk_host0"; + interrupts = ; + clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, + <&cru SCLK_USBPHY0_480M_SRC>; + clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m"; + phys = <&u2phy0_host>; + phy-names = "usb"; status = "disabled"; }; - usb_host1_echi: usb@fe3c0000 { + usb_host1_ehci: usb@fe3c0000 { compatible = "generic-ehci"; reg = <0x0 0xfe3c0000 0x0 0x20000>; - interrupts = ; - clocks = <&cru HCLK_HOST1>; - clock-names = "hclk_host1"; + interrupts = ; + clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>, + <&cru SCLK_USBPHY1_480M_SRC>; + clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m"; + phys = <&u2phy1_host>; + phy-names = "usb"; status = "disabled"; }; usb_host1_ohci: usb@fe3e0000 { compatible = "generic-ohci"; reg = <0x0 0xfe3e0000 0x0 0x20000>; - interrupts = ; - clocks = <&cru HCLK_HOST1>; - clock-names = "hclk_host1"; + interrupts = ; + clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>, + <&cru SCLK_USBPHY1_480M_SRC>; + clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m"; + phys = <&u2phy1_host>; + phy-names = "usb"; + status = "disabled"; + }; + + usbdrd3_0: usb@fe800000 { + compatible = "rockchip,dwc3"; + clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>, + <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>, + <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>; + clock-names = "clk_usb3otg0_ref", "clk_usb3otg0_suspend", + "aclk_usb3otg0", "aclk_usb3_rksoc_axi_perf", + "aclk_usb3", "aclk_usb3_grf"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + usbdrd_dwc3_0: dwc3@fe800000 { + compatible = "snps,dwc3"; + reg = <0x0 0xfe800000 0x0 0x100000>; + interrupts = ; + dr_mode = "otg"; + phys = <&u2phy0_otg>; + phy-names = "usb2-phy"; + snps,dis_enblslpm_quirk; + snps,phyif_utmi_16_bits; + snps,dis_u2_freeclk_exists_quirk; + snps,dis_del_phy_power_chg_quirk; + snps,xhci_slow_suspend_quirk; + status = "disabled"; + }; + }; + + usbdrd3_1: usb@fe900000 { + compatible = "rockchip,dwc3"; + clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>, + <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>, + <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>; + clock-names = "clk_usb3otg1_ref", "clk_usb3otg1_suspend", + "aclk_usb3otg1", "aclk_usb3_rksoc_axi_perf", + "aclk_usb3", "aclk_usb3_grf"; + #address-cells = <2>; + #size-cells = <2>; + ranges; status = "disabled"; + usbdrd_dwc3_1: dwc3@fe900000 { + compatible = "snps,dwc3"; + reg = <0x0 0xfe900000 0x0 0x100000>; + interrupts = ; + dr_mode = "otg"; + phys = <&u2phy1_otg>; + phy-names = "usb2-phy"; + snps,dis_enblslpm_quirk; + snps,phyif_utmi_16_bits; + snps,dis_u2_freeclk_exists_quirk; + snps,dis_del_phy_power_chg_quirk; + snps,xhci_slow_suspend_quirk; + status = "disabled"; + }; }; gic: interrupt-controller@fee00000 { compatible = "arm,gic-v3"; - #interrupt-cells = <3>; + #interrupt-cells = <4>; #address-cells = <2>; #size-cells = <2>; ranges; @@ -337,18 +494,28 @@ <0x0 0xfff00000 0 0x10000>, /* GICC */ <0x0 0xfff10000 0 0x10000>, /* GICH */ <0x0 0xfff20000 0 0x10000>; /* GICV */ - interrupts = ; + interrupts = ; its: interrupt-controller@fee20000 { compatible = "arm,gic-v3-its"; msi-controller; reg = <0x0 0xfee20000 0x0 0x20000>; }; + + ppi-partitions { + part0: interrupt-partition-0 { + affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>; + }; + + part1: interrupt-partition-1 { + affinity = <&cpu_b0 &cpu_b1>; + }; + }; }; saradc: saradc@ff100000 { compatible = "rockchip,rk3399-saradc"; reg = <0x0 0xff100000 0x0 0x100>; - interrupts = ; + interrupts = ; #io-channel-cells = <1>; clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; clock-names = "saradc", "apb_pclk"; @@ -356,11 +523,11 @@ }; i2c0: i2c@ff3c0000 { - compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c"; + compatible = "rockchip,rk3399-i2c"; reg = <0x0 0xff3c0000 0x0 0x1000>; - clocks = <&cru PCLK_I2C0_PMU>, <&cru SCLK_I2C0_PMU>; - clock-names = "i2c", "i2c_sclk"; - interrupts = ; + clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>; + clock-names = "i2c", "pclk"; + interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&i2c0_xfer>; #address-cells = <1>; @@ -369,11 +536,11 @@ }; i2c1: i2c@ff110000 { - compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c"; + compatible = "rockchip,rk3399-i2c"; reg = <0x0 0xff110000 0x0 0x1000>; - clocks = <&cru PCLK_I2C1>, <&cru SCLK_I2C1>; - clock-names = "i2c", "i2c_sclk"; - interrupts = ; + clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; + clock-names = "i2c", "pclk"; + interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&i2c1_xfer>; #address-cells = <1>; @@ -382,11 +549,11 @@ }; i2c2: i2c@ff120000 { - compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c"; + compatible = "rockchip,rk3399-i2c"; reg = <0x0 0xff120000 0x0 0x1000>; - clocks = <&cru PCLK_I2C2>, <&cru SCLK_I2C2>; - clock-names = "i2c", "i2c_sclk"; - interrupts = ; + clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; + clock-names = "i2c", "pclk"; + interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&i2c2_xfer>; #address-cells = <1>; @@ -395,11 +562,11 @@ }; i2c3: i2c@ff130000 { - compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c"; + compatible = "rockchip,rk3399-i2c"; reg = <0x0 0xff130000 0x0 0x1000>; - clocks = <&cru PCLK_I2C3>, <&cru SCLK_I2C3>; - clock-names = "i2c", "i2c_sclk"; - interrupts = ; + clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; + clock-names = "i2c", "pclk"; + interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&i2c3_xfer>; #address-cells = <1>; @@ -408,11 +575,11 @@ }; i2c5: i2c@ff140000 { - compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c"; + compatible = "rockchip,rk3399-i2c"; reg = <0x0 0xff140000 0x0 0x1000>; - clocks = <&cru PCLK_I2C5>, <&cru SCLK_I2C5>; - clock-names = "i2c", "i2c_sclk"; - interrupts = ; + clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>; + clock-names = "i2c", "pclk"; + interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&i2c5_xfer>; #address-cells = <1>; @@ -421,11 +588,11 @@ }; i2c6: i2c@ff150000 { - compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c"; + compatible = "rockchip,rk3399-i2c"; reg = <0x0 0xff150000 0x0 0x1000>; - clocks = <&cru PCLK_I2C6>, <&cru SCLK_I2C6>; - clock-names = "i2c", "i2c_sclk"; - interrupts = ; + clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>; + clock-names = "i2c", "pclk"; + interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&i2c6_xfer>; #address-cells = <1>; @@ -434,11 +601,11 @@ }; i2c7: i2c@ff160000 { - compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c"; + compatible = "rockchip,rk3399-i2c"; reg = <0x0 0xff160000 0x0 0x1000>; - clocks = <&cru PCLK_I2C7>, <&cru SCLK_I2C7>; - clock-names = "i2c", "i2c_sclk"; - interrupts = ; + clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>; + clock-names = "i2c", "pclk"; + interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&i2c7_xfer>; #address-cells = <1>; @@ -451,9 +618,11 @@ reg = <0x0 0xff180000 0x0 0x100>; clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; clock-names = "baudclk", "apb_pclk"; - interrupts = ; + interrupts = ; reg-shift = <2>; reg-io-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; status = "disabled"; }; @@ -462,9 +631,11 @@ reg = <0x0 0xff190000 0x0 0x100>; clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; clock-names = "baudclk", "apb_pclk"; - interrupts = ; + interrupts = ; reg-shift = <2>; reg-io-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_xfer>; status = "disabled"; }; @@ -473,9 +644,11 @@ reg = <0x0 0xff1a0000 0x0 0x100>; clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; clock-names = "baudclk", "apb_pclk"; - interrupts = ; + interrupts = ; reg-shift = <2>; reg-io-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&uart2c_xfer>; status = "disabled"; }; @@ -484,9 +657,11 @@ reg = <0x0 0xff1b0000 0x0 0x100>; clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; clock-names = "baudclk", "apb_pclk"; - interrupts = ; + interrupts = ; reg-shift = <2>; reg-io-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>; status = "disabled"; }; @@ -495,7 +670,7 @@ reg = <0x0 0xff1c0000 0x0 0x1000>; clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; clock-names = "spiclk", "apb_pclk"; - interrupts = ; + interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; #address-cells = <1>; @@ -508,7 +683,7 @@ reg = <0x0 0xff1d0000 0x0 0x1000>; clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; clock-names = "spiclk", "apb_pclk"; - interrupts = ; + interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; #address-cells = <1>; @@ -521,7 +696,7 @@ reg = <0x0 0xff1e0000 0x0 0x1000>; clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; clock-names = "spiclk", "apb_pclk"; - interrupts = ; + interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; #address-cells = <1>; @@ -534,7 +709,7 @@ reg = <0x0 0xff1f0000 0x0 0x1000>; clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>; clock-names = "spiclk", "apb_pclk"; - interrupts = ; + interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>; #address-cells = <1>; @@ -547,7 +722,7 @@ reg = <0x0 0xff200000 0x0 0x1000>; clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>; clock-names = "spiclk", "apb_pclk"; - interrupts = ; + interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>; #address-cells = <1>; @@ -556,15 +731,70 @@ }; thermal-zones { - #include "rk3368-thermal.dtsi" + soc_thermal: soc-thermal { + polling-delay-passive = <20>; /* milliseconds */ + polling-delay = <1000>; /* milliseconds */ + sustainable-power = <1000>; /* milliwatts */ + + thermal-sensors = <&tsadc 0>; + + trips { + threshold: trip-point@0 { + temperature = <70000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + target: trip-point@1 { + temperature = <85000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + soc_crit: soc-crit { + temperature = <95000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&target>; + cooling-device = + <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <4096>; + }; + map1 { + trip = <&target>; + cooling-device = + <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <1024>; + }; + map2 { + trip = <&target>; + cooling-device = + <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <4096>; + }; + }; + }; + + gpu_thermal: gpu-thermal { + polling-delay-passive = <100>; /* milliseconds */ + polling-delay = <1000>; /* milliseconds */ + + thermal-sensors = <&tsadc 1>; + }; }; tsadc: tsadc@ff260000 { compatible = "rockchip,rk3399-tsadc"; reg = <0x0 0xff260000 0x0 0x100>; - interrupts = ; + interrupts = ; + rockchip,grf = <&grf>; clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; clock-names = "tsadc", "apb_pclk"; + assigned-clocks = <&cru SCLK_TSADC>; + assigned-clock-rates = <750000>; resets = <&cru SRST_TSADC>; reset-names = "tsadc-apb"; pinctrl-names = "init", "default", "sleep"; @@ -576,79 +806,289 @@ status = "disabled"; }; - pmu: power-management@ff31000 { + qos_emmc: qos@ffa58000 { + compatible = "syscon"; + reg = <0x0 0xffa58000 0x0 0x20>; + }; + + qos_gmac: qos@ffa5c000 { + compatible = "syscon"; + reg = <0x0 0xffa5c000 0x0 0x20>; + }; + + qos_pcie: qos@ffa60080 { + compatible = "syscon"; + reg = <0x0 0xffa60080 0x0 0x20>; + }; + + qos_usb_host0: qos@ffa60100 { + compatible = "syscon"; + reg = <0x0 0xffa60100 0x0 0x20>; + }; + + qos_usb_host1: qos@ffa60180 { + compatible = "syscon"; + reg = <0x0 0xffa60180 0x0 0x20>; + }; + + qos_usb_otg0: qos@ffa70000 { + compatible = "syscon"; + reg = <0x0 0xffa70000 0x0 0x20>; + }; + + qos_usb_otg1: qos@ffa70080 { + compatible = "syscon"; + reg = <0x0 0xffa70080 0x0 0x20>; + }; + + qos_sd: qos@ffa74000 { + compatible = "syscon"; + reg = <0x0 0xffa74000 0x0 0x20>; + }; + + qos_sdioaudio: qos@ffa76000 { + compatible = "syscon"; + reg = <0x0 0xffa76000 0x0 0x20>; + }; + + qos_hdcp: qos@ffa90000 { + compatible = "syscon"; + reg = <0x0 0xffa90000 0x0 0x20>; + }; + + qos_iep: qos@ffa98000 { + compatible = "syscon"; + reg = <0x0 0xffa98000 0x0 0x20>; + }; + + qos_isp0_m0: qos@ffaa0000 { + compatible = "syscon"; + reg = <0x0 0xffaa0000 0x0 0x20>; + }; + + qos_isp0_m1: qos@ffaa0080 { + compatible = "syscon"; + reg = <0x0 0xffaa0080 0x0 0x20>; + }; + + qos_isp1_m0: qos@ffaa8000 { + compatible = "syscon"; + reg = <0x0 0xffaa8000 0x0 0x20>; + }; + + qos_isp1_m1: qos@ffaa8080 { + compatible = "syscon"; + reg = <0x0 0xffaa8080 0x0 0x20>; + }; + + qos_rga_r: qos@ffab0000 { + compatible = "syscon"; + reg = <0x0 0xffab0000 0x0 0x20>; + }; + + qos_rga_w: qos@ffab0080 { + compatible = "syscon"; + reg = <0x0 0xffab0080 0x0 0x20>; + }; + + qos_video_m0: qos@ffab8000 { + compatible = "syscon"; + reg = <0x0 0xffab8000 0x0 0x20>; + }; + + qos_video_m1_r: qos@ffac0000 { + compatible = "syscon"; + reg = <0x0 0xffac0000 0x0 0x20>; + }; + + qos_video_m1_w: qos@ffac0080 { + compatible = "syscon"; + reg = <0x0 0xffac0080 0x0 0x20>; + }; + + qos_vop_big_r: qos@ffac8000 { + compatible = "syscon"; + reg = <0x0 0xffac8000 0x0 0x20>; + }; + + qos_vop_big_w: qos@ffac8080 { + compatible = "syscon"; + reg = <0x0 0xffac8080 0x0 0x20>; + }; + + qos_vop_little: qos@ffad0000 { + compatible = "syscon"; + reg = <0x0 0xffad0000 0x0 0x20>; + }; + + qos_perihp: qos@ffad8080 { + compatible = "syscon"; + reg = <0x0 0xffad8080 0x0 0x20>; + }; + + qos_gpu: qos@ffae0000 { + compatible = "syscon"; + reg = <0x0 0xffae0000 0x0 0x20>; + }; + + pmu: power-management@ff310000 { compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd"; reg = <0x0 0xff310000 0x0 0x1000>; + /* + * Note: RK3399 supports 6 voltage domains including VD_CORE_L, + * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU. + * Some of the power domains are grouped together for every + * voltage domain. + * The detail contents as below. + */ power: power-controller { - status = "disabled"; compatible = "rockchip,rk3399-power-controller"; #power-domain-cells = <1>; #address-cells = <1>; #size-cells = <0>; - pd_center { - reg = ; - #address-cells = <1>; - #size-cells = <0>; - - pd_vdu { - reg = ; - }; - pd_vcodec { - reg = ; - }; - pd_iep { - reg = ; - }; - pd_rga { - reg = ; - }; - }; - pd_vio { + /* These power domains are grouped by VD_CENTER */ + pd_iep@RK3399_PD_IEP { + reg = ; + clocks = <&cru ACLK_IEP>, + <&cru HCLK_IEP>; + pm_qos = <&qos_iep>; + }; + pd_rga@RK3399_PD_RGA { + reg = ; + clocks = <&cru ACLK_RGA>, + <&cru HCLK_RGA>; + pm_qos = <&qos_rga_r>, + <&qos_rga_w>; + }; + pd_vcodec@RK3399_PD_VCODEC { + reg = ; + clocks = <&cru ACLK_VCODEC>, + <&cru HCLK_VCODEC>; + pm_qos = <&qos_video_m0>; + }; + pd_vdu@RK3399_PD_VDU { + reg = ; + clocks = <&cru ACLK_VDU>, + <&cru HCLK_VDU>; + pm_qos = <&qos_video_m1_r>, + <&qos_video_m1_w>; + }; + + /* These power domains are grouped by VD_GPU */ + pd_gpu@RK3399_PD_GPU { + reg = ; + clocks = <&cru ACLK_GPU>; + pm_qos = <&qos_gpu>; + }; + + /* These power domains are grouped by VD_LOGIC */ + pd_emmc@RK3399_PD_EMMC { + reg = ; + clocks = <&cru ACLK_EMMC>; + pm_qos = <&qos_emmc>; + }; + pd_gmac@RK3399_PD_GMAC { + reg = ; + clocks = <&cru ACLK_GMAC>; + pm_qos = <&qos_gmac>; + }; + pd_perihp@RK3399_PD_PERIHP { + reg = ; + clocks = <&cru ACLK_PERIHP>; + pm_qos = <&qos_perihp>, + <&qos_pcie>, + <&qos_usb_host0>, + <&qos_usb_host1>; + }; + pd_sd@RK3399_PD_SD { + reg = ; + clocks = <&cru HCLK_SDMMC>; + pm_qos = <&qos_sd>; + }; + pd_sdioaudio@RK3399_PD_SDIOAUDIO { + reg = ; + clocks = <&cru HCLK_SDIO>; + pm_qos = <&qos_sdioaudio>; + }; + pd_usb3@RK3399_PD_USB3 { + reg = ; + clocks = <&cru ACLK_USB3>; + pm_qos = <&qos_usb_otg0>, + <&qos_usb_otg1>; + }; + pd_vio@RK3399_PD_VIO { reg = ; #address-cells = <1>; #size-cells = <0>; - pd_isp0 { + pd_hdcp@RK3399_PD_HDCP { + reg = ; + clocks = <&cru ACLK_HDCP>, + <&cru HCLK_HDCP>, + <&cru PCLK_HDCP>; + pm_qos = <&qos_hdcp>; + }; + pd_isp0@RK3399_PD_ISP0 { reg = ; + clocks = <&cru ACLK_ISP0>, + <&cru HCLK_ISP0>; + pm_qos = <&qos_isp0_m0>, + <&qos_isp0_m1>; }; - pd_isp1 { + pd_isp1@RK3399_PD_ISP1 { reg = ; + clocks = <&cru ACLK_ISP1>, + <&cru HCLK_ISP1>; + pm_qos = <&qos_isp1_m0>, + <&qos_isp1_m1>; }; - pd_hdcp { - reg = ; - }; - pd_vo { + pd_vo@RK3399_PD_VO { reg = ; #address-cells = <1>; #size-cells = <0>; - pd_vopb { + pd_vopb@RK3399_PD_VOPB { reg = ; + clocks = <&cru ACLK_VOP0>, + <&cru HCLK_VOP0>; + pm_qos = <&qos_vop_big_r>, + <&qos_vop_big_w>; }; - pd_vopl { + pd_vopl@RK3399_PD_VOPL { reg = ; + clocks = <&cru ACLK_VOP1>, + <&cru HCLK_VOP1>; + pm_qos = <&qos_vop_little>; }; }; }; - pd_gpu { - reg = ; - }; }; }; pmugrf: syscon@ff320000 { - compatible = "rockchip,rk3399-pmugrf", "syscon"; + compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd"; reg = <0x0 0xff320000 0x0 0x1000>; + + reboot-mode { + compatible = "syscon-reboot-mode"; + offset = <0x300>; + mode-bootloader = ; + mode-charge = ; + mode-fastboot = ; + mode-loader = ; + mode-normal = ; + mode-recovery = ; + }; }; spi3: spi@ff350000 { compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; reg = <0x0 0xff350000 0x0 0x1000>; - clocks = <&cru SCLK_SPI3_PMU>, <&cru PCLK_SPI3_PMU>; + clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>; clock-names = "spiclk", "apb_pclk"; - interrupts = ; + interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>; #address-cells = <1>; @@ -659,20 +1099,22 @@ uart4: serial@ff370000 { compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; reg = <0x0 0xff370000 0x0 0x100>; - clocks = <&cru SCLK_UART4_PMU>, <&cru PCLK_UART4_PMU>; + clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>; clock-names = "baudclk", "apb_pclk"; - interrupts = ; + interrupts = ; reg-shift = <2>; reg-io-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&uart4_xfer>; status = "disabled"; }; i2c4: i2c@ff3d0000 { - compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c"; + compatible = "rockchip,rk3399-i2c"; reg = <0x0 0xff3d0000 0x0 0x1000>; - clocks = <&cru PCLK_I2C4_PMU>, <&cru SCLK_I2C4_PMU>; - clock-names = "i2c", "i2c_sclk"; - interrupts = ; + clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>; + clock-names = "i2c", "pclk"; + interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&i2c4_xfer>; #address-cells = <1>; @@ -681,11 +1123,11 @@ }; i2c8: i2c@ff3e0000 { - compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c"; + compatible = "rockchip,rk3399-i2c"; reg = <0x0 0xff3e0000 0x0 0x1000>; - clocks = <&cru PCLK_I2C8_PMU>, <&cru SCLK_I2C8_PMU>; - clock-names = "i2c", "i2c_sclk"; - interrupts = ; + clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>; + clock-names = "i2c", "pclk"; + interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&i2c8_xfer>; #address-cells = <1>; @@ -693,13 +1135,56 @@ status = "disabled"; }; + pcie0: pcie@f8000000 { + compatible = "rockchip,rk3399-pcie"; + #address-cells = <3>; + #size-cells = <2>; + clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>, + <&cru PCLK_PCIE>, <&cru SCLK_PCIEPHY_REF>; + clock-names = "aclk_pcie", "aclk_perf_pcie", + "hclk_pcie", "clk_pciephy_ref"; + bus-range = <0x0 0x1>; + interrupts = , + , + ; + interrupt-names = "pcie-sys", "pcie-legacy", "pcie-client"; + ranges = < 0x82000000 0 0xfa000000 0x0 0xfa000000 0 0x600000 + 0x81000000 0 0xfa600000 0x0 0xfa600000 0 0x100000 >; + reg = < 0x0 0xf8000000 0x0 0x2000000 >, + < 0x0 0xfd000000 0x0 0x1000000 >; + reg-name = "axi-base", "apb-base"; + resets = <&cru SRST_PCIEPHY>, <&cru SRST_PCIE_CORE>, + <&cru SRST_PCIE_MGMT>, <&cru SRST_PCIE_MGMT_STICKY>, + <&cru SRST_PCIE_PIPE>; + reset-names = "phy-rst", "core-rst", "mgmt-rst", + "mgmt-sticky-rst", "pipe-rst"; + rockchip,grf = <&grf>; + pcie-conf = <0xe220>; + pcie-status = <0xe2a4>; + pcie-laneoff = <0xe214>; + power-domains = <&power RK3399_PD_PERIHP>; + msi-parent = <&its>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie0 1>, + <0 0 0 2 &pcie0 2>, + <0 0 0 3 &pcie0 3>, + <0 0 0 4 &pcie0 4>; + status = "disabled"; + pcie_intc: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + pwm0: pwm@ff420000 { compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; reg = <0x0 0xff420000 0x0 0x10>; #pwm-cells = <3>; pinctrl-names = "default"; pinctrl-0 = <&pwm0_pin>; - clocks = <&cru PCLK_RKPWM_PMU>; + clocks = <&pmucru PCLK_RKPWM_PMU>; clock-names = "pwm"; status = "disabled"; }; @@ -710,7 +1195,7 @@ #pwm-cells = <3>; pinctrl-names = "default"; pinctrl-0 = <&pwm1_pin>; - clocks = <&cru PCLK_RKPWM_PMU>; + clocks = <&pmucru PCLK_RKPWM_PMU>; clock-names = "pwm"; status = "disabled"; }; @@ -721,7 +1206,7 @@ #pwm-cells = <3>; pinctrl-names = "default"; pinctrl-0 = <&pwm2_pin>; - clocks = <&cru PCLK_RKPWM_PMU>; + clocks = <&pmucru PCLK_RKPWM_PMU>; clock-names = "pwm"; status = "disabled"; }; @@ -732,48 +1217,186 @@ #pwm-cells = <3>; pinctrl-names = "default"; pinctrl-0 = <&pwm3a_pin>; - clocks = <&cru PCLK_RKPWM_PMU>; + clocks = <&pmucru PCLK_RKPWM_PMU>; clock-names = "pwm"; status = "disabled"; }; + rga: rga@ff680000 { + compatible = "rockchip,rk3399-rga"; + reg = <0x0 0xff680000 0x0 0x10000>; + interrupts = ; + interrupt-names = "rga"; + clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>; + clock-names = "aclk", "hclk", "sclk"; + resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>; + reset-names = "core", "axi", "ahb"; + power-domains = <&power RK3399_PD_RGA>; + status = "disabled"; + }; + pmucru: pmu-clock-controller@ff750000 { compatible = "rockchip,rk3399-pmucru"; reg = <0x0 0xff750000 0x0 0x1000>; - rockchip,grf = <&pmugrf>; #clock-cells = <1>; #reset-cells = <1>; + assigned-clocks = <&pmucru PLL_PPLL>; + assigned-clock-rates = <676000000>; }; cru: clock-controller@ff760000 { compatible = "rockchip,rk3399-cru"; reg = <0x0 0xff760000 0x0 0x1000>; - rockchip,grf = <&grf>; #clock-cells = <1>; #reset-cells = <1>; + assigned-clocks = + <&cru ACLK_VOP0>, <&cru HCLK_VOP0>, + <&cru ACLK_VOP1>, <&cru HCLK_VOP1>, + <&cru ARMCLKL>, <&cru ARMCLKB>, + <&cru PLL_GPLL>, <&cru PLL_CPLL>, + <&cru PLL_NPLL>, + <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>, + <&cru PCLK_PERIHP>, + <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, + <&cru PCLK_PERILP0>, + <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>; + assigned-clock-rates = + <400000000>, <200000000>, + <400000000>, <200000000>, + <816000000>, <816000000>, + <594000000>, <800000000>, + <1000000000>, + <150000000>, <75000000>, + <37500000>, + <100000000>, <100000000>, + <50000000>, + <100000000>, <50000000>; }; grf: syscon@ff770000 { - compatible = "rockchip,rk3399-grf", "syscon"; + compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; reg = <0x0 0xff770000 0x0 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + + u2phy0: usb2-phy@e450 { + compatible = "rockchip,rk3399-usb2phy"; + reg = <0xe450 0x10>; + clocks = <&cru SCLK_USB2PHY0_REF>; + clock-names = "phyclk"; + #clock-cells = <0>; + clock-output-names = "clk_usbphy0_480m"; + status = "disabled"; + + u2phy0_otg: otg-port { + #phy-cells = <0>; + interrupts = , + , + ; + interrupt-names = "otg-bvalid", "otg-id", + "linestate"; + status = "disabled"; + }; + + u2phy0_host: host-port { + #phy-cells = <0>; + interrupts = ; + interrupt-names = "linestate"; + status = "disabled"; + }; + }; + + u2phy1: usb2-phy@e460 { + compatible = "rockchip,rk3399-usb2phy"; + reg = <0xe460 0x10>; + clocks = <&cru SCLK_USB2PHY1_REF>; + clock-names = "phyclk"; + #clock-cells = <0>; + clock-output-names = "clk_usbphy1_480m"; + status = "disabled"; + + u2phy1_otg: otg-port { + #phy-cells = <0>; + interrupts = , + , + ; + interrupt-names = "otg-bvalid", "otg-id", + "linestate"; + status = "disabled"; + }; + + u2phy1_host: host-port { + #phy-cells = <0>; + interrupts = ; + interrupt-names = "linestate"; + status = "disabled"; + }; + }; + }; + + tcphy0: phy@ff7c0000 { + compatible = "rockchip,rk3399-typec-phy"; + reg = <0x0 0xff7c0000 0x0 0x40000>; + rockchip,grf = <&grf>; + #phy-cells = <0>; + clocks = <&cru SCLK_UPHY0_TCPDCORE>, + <&cru SCLK_UPHY0_TCPDPHY_REF>; + clock-names = "tcpdcore", "tcpdphy-ref"; + resets = <&cru SRST_UPHY0>, + <&cru SRST_UPHY0_PIPE_L00>, + <&cru SRST_P_UPHY0_TCPHY>; + reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; + rockchip,typec-conn-dir = <0xe580 0 16>; + rockchip,usb3tousb2-en = <0xe580 3 19>; + rockchip,external-psm = <0xe588 14 30>; + rockchip,pipe-status = <0xe5c0 0 0>; + rockchip,uphy-dp-sel = <0x6268 19 19>; + status = "disabled"; }; - wdt0: watchdog@ff840000 { + tcphy1: phy@ff800000 { + compatible = "rockchip,rk3399-typec-phy"; + reg = <0x0 0xff800000 0x0 0x40000>; + rockchip,grf = <&grf>; + #phy-cells = <0>; + clocks = <&cru SCLK_UPHY1_TCPDCORE>, + <&cru SCLK_UPHY1_TCPDPHY_REF>; + clock-names = "tcpdcore", "tcpdphy-ref"; + resets = <&cru SRST_UPHY1>, + <&cru SRST_UPHY1_PIPE_L00>, + <&cru SRST_P_UPHY1_TCPHY>; + reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; + rockchip,typec-conn-dir = <0xe58c 0 16>; + rockchip,usb3tousb2-en = <0xe58c 3 19>; + rockchip,external-psm = <0xe594 14 30>; + rockchip,pipe-status = <0xe5c0 16 16>; + rockchip,uphy-dp-sel = <0x6268 3 19>; + status = "disabled"; + }; + + watchdog@ff840000 { compatible = "snps,dw-wdt"; reg = <0x0 0xff840000 0x0 0x100>; clocks = <&cru PCLK_WDT>; - interrupts = ; - status = "disabled"; + interrupts = ; + }; + + rktimer: rktimer@ff850000 { + compatible = "rockchip,rk3399-timer"; + reg = <0x0 0xff850000 0x0 0x1000>; + interrupts = ; + clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>; + clock-names = "pclk", "timer"; }; spdif: spdif@ff870000 { compatible = "rockchip,rk3399-spdif"; reg = <0x0 0xff870000 0x0 0x1000>; - interrupts = ; + interrupts = ; dmas = <&dmac_bus 7>; dma-names = "tx"; - clock-names = "hclk", "mclk"; - clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF_8CH>; + clock-names = "mclk", "hclk"; + clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>; pinctrl-names = "default"; pinctrl-0 = <&spdif_bus>; status = "disabled"; @@ -782,13 +1405,12 @@ i2s0: i2s@ff880000 { compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; reg = <0x0 0xff880000 0x0 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; + rockchip,grf = <&grf>; + interrupts = ; dmas = <&dmac_bus 0>, <&dmac_bus 1>; dma-names = "tx", "rx"; - clock-names = "i2s_hclk", "i2s_clk"; - clocks = <&cru HCLK_I2S0_8CH>, <&cru SCLK_I2S0_8CH>; + clock-names = "i2s_clk", "i2s_hclk"; + clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>; pinctrl-names = "default"; pinctrl-0 = <&i2s0_8ch_bus>; status = "disabled"; @@ -797,13 +1419,11 @@ i2s1: i2s@ff890000 { compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; reg = <0x0 0xff890000 0x0 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; + interrupts = ; dmas = <&dmac_bus 2>, <&dmac_bus 3>; dma-names = "tx", "rx"; - clock-names = "i2s_hclk", "i2s_clk"; - clocks = <&cru HCLK_I2S1_8CH>, <&cru SCLK_I2S1_8CH>; + clock-names = "i2s_clk", "i2s_hclk"; + clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>; pinctrl-names = "default"; pinctrl-0 = <&i2s1_2ch_bus>; status = "disabled"; @@ -812,13 +1432,248 @@ i2s2: i2s@ff8a0000 { compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; reg = <0x0 0xff8a0000 0x0 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; + interrupts = ; dmas = <&dmac_bus 4>, <&dmac_bus 5>; dma-names = "tx", "rx"; - clock-names = "i2s_hclk", "i2s_clk"; - clocks = <&cru HCLK_I2S2_8CH>, <&cru SCLK_I2S2_8CH>; + clock-names = "i2s_clk", "i2s_hclk"; + clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>; + status = "disabled"; + }; + + gpu: gpu@ff9a0000 { + compatible = "arm,malit860", + "arm,malit86x", + "arm,malit8xx", + "arm,mali-midgard"; + + reg = <0x0 0xff9a0000 0x0 0x10000>; + + interrupts = , + , + ; + interrupt-names = "GPU", "JOB", "MMU"; + + clocks = <&cru ACLK_GPU>; + clock-names = "clk_mali"; + #cooling-cells = <2>; /* min followed by max */ + operating-points-v2 = <&gpu_opp_table>; + power-domains = <&power RK3399_PD_GPU>; + power-off-delay-ms = <200>; + status = "disabled"; + + gpu_power_model: power_model { + compatible = "arm,mali-simple-power-model"; + voltage = <900>; + frequency = <500>; + static-power = <300>; + dynamic-power = <396>; + ts = <32000 4700 (-80) 2>; + thermal-zone = "gpu-thermal"; + }; + }; + + gpu_opp_table: gpu_opp_table { + compatible = "operating-points-v2"; + opp-shared; + + opp@200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <900000>; + }; + opp@300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <900000>; + }; + opp@400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <900000>; + }; + + }; + + vopl: vop@ff8f0000 { + compatible = "rockchip,rk3399-vop-lit"; + reg = <0x0 0xff8f0000 0x0 0x3efc>; + interrupts = ; + clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>; + clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; + resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>; + reset-names = "axi", "ahb", "dclk"; + power-domains = <&power RK3399_PD_VOPL>; + iommus = <&vopl_mmu>; + status = "disabled"; + + vopl_out: port { + #address-cells = <1>; + #size-cells = <0>; + + vopl_out_mipi: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_in_vopl>; + }; + + vopl_out_edp: endpoint@1 { + reg = <1>; + remote-endpoint = <&edp_in_vopl>; + }; + + vopl_out_hdmi: endpoint@2 { + reg = <2>; + remote-endpoint = <&hdmi_in_vopl>; + }; + }; + }; + + vopl_mmu: iommu@ff8f3f00 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff8f3f00 0x0 0x100>; + interrupts = ; + interrupt-names = "vopl_mmu"; + #iommu-cells = <0>; + status = "disabled"; + }; + + vopb: vop@ff900000 { + compatible = "rockchip,rk3399-vop-big"; + reg = <0x0 0xff900000 0x0 0x3efc>; + interrupts = ; + clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; + clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; + resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>; + reset-names = "axi", "ahb", "dclk"; + power-domains = <&power RK3399_PD_VOPB>; + iommus = <&vopb_mmu>; + status = "disabled"; + + vopb_out: port { + #address-cells = <1>; + #size-cells = <0>; + + vopb_out_edp: endpoint@0 { + reg = <0>; + remote-endpoint = <&edp_in_vopb>; + }; + + vopb_out_mipi: endpoint@1 { + reg = <1>; + remote-endpoint = <&mipi_in_vopb>; + }; + + vopb_out_hdmi: endpoint@2 { + reg = <2>; + remote-endpoint = <&hdmi_in_vopb>; + }; + }; + }; + + vopb_mmu: iommu@ff903f00 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff903f00 0x0 0x100>; + interrupts = ; + interrupt-names = "vopb_mmu"; + #iommu-cells = <0>; + status = "disabled"; + }; + + hdmi: hdmi@ff940000 { + compatible = "rockchip,rk3399-dw-hdmi"; + reg = <0x0 0xff940000 0x0 0x20000>; + reg-io-width = <4>; + rockchip,grf = <&grf>; + power-domains = <&power RK3399_PD_HDCP>; + interrupts = ; + clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, <&cru SCLK_HDMI_SFR>, <&cru PCLK_EDP_CTRL>; + clock-names = "iahb", "isfr", "vpll", "grf"; + status = "disabled"; + + ports { + hdmi_in: port { + #address-cells = <1>; + #size-cells = <0>; + hdmi_in_vopb: endpoint@0 { + reg = <0>; + remote-endpoint = <&vopb_out_hdmi>; + }; + hdmi_in_vopl: endpoint@1 { + reg = <1>; + remote-endpoint = <&vopl_out_hdmi>; + }; + }; + }; + }; + + mipi_dsi: mipi@ff960000 { + compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"; + reg = <0x0 0xff960000 0x0 0x8000>; + interrupts = ; + clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>, + <&cru SCLK_DPHY_TX0_CFG>; + clock-names = "ref", "pclk", "phy_cfg"; + power-domains = <&power RK3399_PD_VIO>; + rockchip,grf = <&grf>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + mipi_in: port { + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_vopb: endpoint@0 { + reg = <0>; + remote-endpoint = <&vopb_out_mipi>; + }; + mipi_in_vopl: endpoint@1 { + reg = <1>; + remote-endpoint = <&vopl_out_mipi>; + }; + }; + }; + }; + + edp: edp@ff970000 { + compatible = "rockchip,rk3399-edp"; + reg = <0x0 0xff970000 0x0 0x8000>; + interrupts = ; + clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>; + clock-names = "dp", "pclk"; + resets = <&cru SRST_P_EDP_CTRL>; + reset-names = "dp"; + rockchip,grf = <&grf>; + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&edp_hpd>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + edp_in: port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + edp_in_vopb: endpoint@0 { + reg = <0>; + remote-endpoint = <&vopb_out_edp>; + }; + + edp_in_vopl: endpoint@1 { + reg = <1>; + remote-endpoint = <&vopl_out_edp>; + }; + }; + }; + }; + + display_subsystem: display-subsystem { + compatible = "rockchip,display-subsystem"; + ports = <&vopl_out>, <&vopb_out>; status = "disabled"; }; @@ -833,8 +1688,8 @@ gpio0: gpio0@ff720000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xff720000 0x0 0x100>; - clocks = <&xin24m>; - interrupts = ; + clocks = <&pmucru PCLK_GPIO0_PMU>; + interrupts = ; gpio-controller; #gpio-cells = <0x2>; @@ -846,8 +1701,8 @@ gpio1: gpio1@ff730000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xff730000 0x0 0x100>; - clocks = <&xin24m>; - interrupts = ; + clocks = <&pmucru PCLK_GPIO1_PMU>; + interrupts = ; gpio-controller; #gpio-cells = <0x2>; @@ -859,8 +1714,8 @@ gpio2: gpio2@ff780000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xff780000 0x0 0x100>; - clocks = <&xin24m>; - interrupts = ; + clocks = <&cru PCLK_GPIO2>; + interrupts = ; gpio-controller; #gpio-cells = <0x2>; @@ -872,8 +1727,8 @@ gpio3: gpio3@ff788000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xff788000 0x0 0x100>; - clocks = <&xin24m>; - interrupts = ; + clocks = <&cru PCLK_GPIO3>; + interrupts = ; gpio-controller; #gpio-cells = <0x2>; @@ -885,8 +1740,8 @@ gpio4: gpio4@ff790000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xff790000 0x0 0x100>; - clocks = <&xin24m>; - interrupts = ; + clocks = <&cru PCLK_GPIO4>; + interrupts = ; gpio-controller; #gpio-cells = <0x2>; @@ -907,6 +1762,21 @@ bias-disable; }; + pcfg_pull_up_20ma: pcfg-pull-up-20ma { + bias-pull-up; + drive-strength = <20>; + }; + + pcfg_pull_none_20ma: pcfg-pull-none-20ma { + bias-disable; + drive-strength = <20>; + }; + + pcfg_pull_none_18ma: pcfg-pull-none-18ma { + bias-disable; + drive-strength = <18>; + }; + pcfg_pull_none_12ma: pcfg-pull-none-12ma { bias-disable; drive-strength = <12>; @@ -932,6 +1802,11 @@ drive-strength = <12>; }; + pcfg_pull_none_13ma: pcfg-pull-none-13ma { + bias-disable; + drive-strength = <13>; + }; + emmc { emmc_pwr: emmc-pwr { rockchip,pins = @@ -942,35 +1817,60 @@ gmac { rgmii_pins: rgmii-pins { rockchip,pins = - <3 11 RK_FUNC_1 &pcfg_pull_none>, + /* mac_txclk */ + <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>, + /* mac_rxclk */ + <3 14 RK_FUNC_1 &pcfg_pull_none>, + /* mac_mdio */ <3 13 RK_FUNC_1 &pcfg_pull_none>, + /* mac_txen */ + <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>, + /* mac_clk */ + <3 11 RK_FUNC_1 &pcfg_pull_none>, + /* mac_rxdv */ + <3 9 RK_FUNC_1 &pcfg_pull_none>, + /* mac_mdc */ <3 8 RK_FUNC_1 &pcfg_pull_none>, - <3 4 RK_FUNC_1 &pcfg_pull_none_12ma>, - <3 5 RK_FUNC_1 &pcfg_pull_none_12ma>, - <3 0 RK_FUNC_1 &pcfg_pull_none_12ma>, - <3 1 RK_FUNC_1 &pcfg_pull_none_12ma>, - <3 17 RK_FUNC_1 &pcfg_pull_none_12ma>, - <3 12 RK_FUNC_1 &pcfg_pull_none_12ma>, - <3 6 RK_FUNC_1 &pcfg_pull_none>, + /* mac_rxd1 */ <3 7 RK_FUNC_1 &pcfg_pull_none>, - <3 2 RK_FUNC_1 &pcfg_pull_none>, + /* mac_rxd0 */ + <3 6 RK_FUNC_1 &pcfg_pull_none>, + /* mac_txd1 */ + <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>, + /* mac_txd0 */ + <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>, + /* mac_rxd3 */ <3 3 RK_FUNC_1 &pcfg_pull_none>, - <3 14 RK_FUNC_1 &pcfg_pull_none>, - <3 9 RK_FUNC_1 &pcfg_pull_none>; + /* mac_rxd2 */ + <3 2 RK_FUNC_1 &pcfg_pull_none>, + /* mac_txd3 */ + <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>, + /* mac_txd2 */ + <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>; }; rmii_pins: rmii-pins { rockchip,pins = - <3 11 RK_FUNC_1 &pcfg_pull_none>, + /* mac_mdio */ <3 13 RK_FUNC_1 &pcfg_pull_none>, + /* mac_txen */ + <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>, + /* mac_clk */ + <3 11 RK_FUNC_1 &pcfg_pull_none>, + /* mac_rxer */ + <3 10 RK_FUNC_1 &pcfg_pull_none>, + /* mac_rxdv */ + <3 9 RK_FUNC_1 &pcfg_pull_none>, + /* mac_mdc */ <3 8 RK_FUNC_1 &pcfg_pull_none>, - <3 4 RK_FUNC_1 &pcfg_pull_none_12ma>, - <3 5 RK_FUNC_1 &pcfg_pull_none_12ma>, - <3 12 RK_FUNC_1 &pcfg_pull_none_12ma>, - <3 6 RK_FUNC_1 &pcfg_pull_none>, + /* mac_rxd1 */ <3 7 RK_FUNC_1 &pcfg_pull_none>, - <3 9 RK_FUNC_1 &pcfg_pull_none>, - <3 10 RK_FUNC_1 &pcfg_pull_none>; + /* mac_rxd0 */ + <3 6 RK_FUNC_1 &pcfg_pull_none>, + /* mac_txd1 */ + <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>, + /* mac_txd0 */ + <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>; }; }; @@ -1004,6 +1904,13 @@ <4 17 RK_FUNC_1 &pcfg_pull_none>, <4 16 RK_FUNC_1 &pcfg_pull_none>; }; + + i2c3_gpio: i2c3_gpio { + rockchip,pins = + <4 17 RK_FUNC_GPIO &pcfg_pull_none>, + <4 16 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; i2c4 { @@ -1162,6 +2069,11 @@ rockchip,pins = <4 21 RK_FUNC_1 &pcfg_pull_none>; }; + + spdif_bus_1: spdif-bus-1 { + rockchip,pins = + <3 16 RK_FUNC_3 &pcfg_pull_none>; + }; }; spi0 { @@ -1421,10 +2333,35 @@ }; }; - pmic { - pmic_int_l: pmic-int-l { + edp { + edp_hpd: edp-hpd { + rockchip,pins = + <4 23 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + hdmi { + hdmi_i2c_xfer: hdmi-i2c-xfer { + rockchip,pins = + <4 17 RK_FUNC_3 &pcfg_pull_none>, + <4 16 RK_FUNC_3 &pcfg_pull_none>; + }; + + hdmi_cec: hdmi-cec { + rockchip,pins = + <4 23 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + pcie { + pcie_clkreqn: pci-clkreqn { + rockchip,pins = + <2 26 RK_FUNC_2 &pcfg_pull_none>; + }; + + pcie_clkreqnb: pci-clkreqnb { rockchip,pins = - <1 21 RK_FUNC_GPIO &pcfg_pull_up>; + <4 24 RK_FUNC_1 &pcfg_pull_none>; }; }; };