X-Git-Url: http://plrg.eecs.uci.edu/git/?p=firefly-linux-kernel-4.4.55.git;a=blobdiff_plain;f=arch%2Farm64%2Fboot%2Fdts%2Frockchip%2Frk3368.dtsi;h=57bd06f0c1f6c796a166ebbd5f49e73cd9fad0fc;hp=a433fbd0feac3916957e195a91c9525688af5c84;hb=e84c207ab2ba43c5095e0c263f6844c8c4303815;hpb=4aa052224404dec656968fa9e35685433c05265e diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi index a433fbd0feac..57bd06f0c1f6 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi @@ -45,7 +45,12 @@ #include #include #include -#include +#include +#include +#include +#include +#include +#include / { compatible = "rockchip,rk3368"; @@ -54,6 +59,7 @@ #size-cells = <2>; aliases { + ethernet0 = &gmac; i2c0 = &i2c0; i2c1 = &i2c1; i2c2 = &i2c2; @@ -68,7 +74,6 @@ spi0 = &spi0; spi1 = &spi1; spi2 = &spi2; - lcdc = &lcdc; }; cpus { @@ -78,109 +83,319 @@ cpu-map { cluster0 { core0 { - cpu = <&cpu_b0>; + cpu = <&cpu_l0>; }; core1 { - cpu = <&cpu_b1>; + cpu = <&cpu_l1>; }; core2 { - cpu = <&cpu_b2>; + cpu = <&cpu_l2>; }; core3 { - cpu = <&cpu_b3>; + cpu = <&cpu_l3>; }; }; cluster1 { core0 { - cpu = <&cpu_l0>; + cpu = <&cpu_b0>; }; core1 { - cpu = <&cpu_l1>; + cpu = <&cpu_b1>; }; core2 { - cpu = <&cpu_l2>; + cpu = <&cpu_b2>; }; core3 { - cpu = <&cpu_l3>; + cpu = <&cpu_b3>; }; }; }; - idle-states { - entry-method = "psci"; - - cpu_sleep: cpu-sleep-0 { - compatible = "arm,idle-state"; - arm,psci-suspend-param = <0x1010000>; - entry-latency-us = <0x3fffffff>; - exit-latency-us = <0x40000000>; - min-residency-us = <0xffffffff>; - }; - }; - cpu_l0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x0>; - cpu-idle-states = <&cpu_sleep>; enable-method = "psci"; + clocks = <&cru ARMCLKL>; + next-level-cache = <&cluster0_l2>; + operating-points-v2 = <&cluster0_opp>; + sched-energy-costs = <&RK3368_CPU_COST_0 &RK3368_CLUSTER_COST_0>; + #cooling-cells = <2>; /* min followed by max */ + dynamic-power-coefficient = <149>; }; cpu_l1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x1>; - cpu-idle-states = <&cpu_sleep>; enable-method = "psci"; + clocks = <&cru ARMCLKL>; + next-level-cache = <&cluster0_l2>; + operating-points-v2 = <&cluster0_opp>; + sched-energy-costs = <&RK3368_CPU_COST_0 &RK3368_CLUSTER_COST_0>; }; cpu_l2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x2>; - cpu-idle-states = <&cpu_sleep>; enable-method = "psci"; + clocks = <&cru ARMCLKL>; + next-level-cache = <&cluster0_l2>; + operating-points-v2 = <&cluster0_opp>; + sched-energy-costs = <&RK3368_CPU_COST_0 &RK3368_CLUSTER_COST_0>; }; cpu_l3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x3>; - cpu-idle-states = <&cpu_sleep>; enable-method = "psci"; + clocks = <&cru ARMCLKL>; + next-level-cache = <&cluster0_l2>; + operating-points-v2 = <&cluster0_opp>; + sched-energy-costs = <&RK3368_CPU_COST_0 &RK3368_CLUSTER_COST_0>; }; cpu_b0: cpu@100 { device_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x100>; - cpu-idle-states = <&cpu_sleep>; enable-method = "psci"; + clocks = <&cru ARMCLKB>; + next-level-cache = <&cluster1_l2>; + operating-points-v2 = <&cluster1_opp>; + sched-energy-costs = <&RK3368_CPU_COST_1 &RK3368_CLUSTER_COST_1>; + #cooling-cells = <2>; /* min followed by max */ + dynamic-power-coefficient = <160>; }; cpu_b1: cpu@101 { device_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x101>; - cpu-idle-states = <&cpu_sleep>; enable-method = "psci"; + clocks = <&cru ARMCLKB>; + next-level-cache = <&cluster1_l2>; + operating-points-v2 = <&cluster1_opp>; + sched-energy-costs = <&RK3368_CPU_COST_1 &RK3368_CLUSTER_COST_1>; }; cpu_b2: cpu@102 { device_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x102>; - cpu-idle-states = <&cpu_sleep>; enable-method = "psci"; + clocks = <&cru ARMCLKB>; + next-level-cache = <&cluster1_l2>; + operating-points-v2 = <&cluster1_opp>; + sched-energy-costs = <&RK3368_CPU_COST_1 &RK3368_CLUSTER_COST_1>; }; cpu_b3: cpu@103 { device_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x103>; - cpu-idle-states = <&cpu_sleep>; enable-method = "psci"; + clocks = <&cru ARMCLKB>; + next-level-cache = <&cluster1_l2>; + operating-points-v2 = <&cluster1_opp>; + sched-energy-costs = <&RK3368_CPU_COST_1 &RK3368_CLUSTER_COST_1>; + }; + + cluster0_l2: l2-cache0 { + compatible = "cache"; + }; + + cluster1_l2: l2-cache1 { + compatible = "cache"; + }; + }; + + cluster0_opp: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp@216000000 { + opp-hz = /bits/ 64 <216000000>; + opp-microvolt = <950000 950000 1350000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + opp@408000000 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <950000 950000 1350000>; + clock-latency-ns = <40000>; + }; + opp@600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <950000 950000 1350000>; + clock-latency-ns = <40000>; + }; + opp@816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <1025000 1025000 1350000>; + clock-latency-ns = <40000>; + }; + opp@1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <1125000 1125000 1350000>; + clock-latency-ns = <40000>; + }; + opp@1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1225000 1225000 1350000>; + clock-latency-ns = <40000>; + }; + }; + + cluster1_opp: opp_table1 { + compatible = "operating-points-v2"; + opp-shared; + + opp@216000000 { + opp-hz = /bits/ 64 <216000000>; + opp-microvolt = <950000 950000 1350000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + opp@408000000 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <950000 950000 1350000>; + clock-latency-ns = <40000>; + }; + opp@600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <950000 950000 1350000>; + clock-latency-ns = <40000>; + }; + opp@816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <975000 975000 1350000>; + clock-latency-ns = <40000>; + }; + opp@1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <1050000 1050000 1350000>; + clock-latency-ns = <40000>; + }; + opp@1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1150000 1150000 1350000>; + clock-latency-ns = <40000>; + }; + opp@1296000000 { + opp-hz = /bits/ 64 <1296000000>; + opp-microvolt = <1225000 1225000 1350000>; + clock-latency-ns = <40000>; + }; + opp@1416000000 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <1300000 1300000 1350000>; + clock-latency-ns = <40000>; + }; + opp@1512000000 { + opp-hz = /bits/ 64 <1512000000>; + opp-microvolt = <1350000 1350000 1350000>; + clock-latency-ns = <40000>; + }; + }; + + energy-costs { + RK3368_CPU_COST_0: rk3368-core-cost0 { + busy-cost-data = < + 146 44 /* 216M */ + 276 72 /* 408M */ + 406 99 /* 600M */ + 552 147 /* 816M */ + 682 200 /* 1008M */ + 812 255 /* 1200M */ + >; + idle-cost-data = < + 6 + 6 + 0 + >; + }; + + RK3368_CPU_COST_1: rk3368-core-cost1 { + busy-cost-data = < + 146 53 /* 216M */ + 276 86 /* 408M */ + 406 118 /* 600M */ + 552 166 /* 816M */ + 682 226 /* 1008M */ + 812 309 /* 1200M */ + 878 371 /* 1200M */ + 959 446 /* 1416M */ + 1024 513 /* 1512M */ + >; + idle-cost-data = < + 6 + 6 + 0 + >; + }; + + RK3368_CLUSTER_COST_0: rk3368-cluster-cost0 { + busy-cost-data = < + 146 9 /* 216M */ + 276 14 /* 408M */ + 406 20 /* 600M */ + 552 29 /* 816M */ + 682 40 /* 1008M */ + 812 51 /* 1200M */ + >; + idle-cost-data = < + 56 + 56 + 56 + >; + }; + + RK3368_CLUSTER_COST_1: rk3368-cluster-cost1 { + busy-cost-data = < + 146 11 /* 216M */ + 276 17 /* 408M */ + 406 24 /* 600M */ + 552 33 /* 816M */ + 682 45 /* 1008M */ + 812 62 /* 1200M */ + 878 74 /* 1200M */ + 959 89 /* 1416M */ + 1024 103 /* 1512M */ + >; + idle-cost-data = < + 56 + 56 + 56 + >; + }; + }; + + cpu_avs: cpu-avs { + cluster0-avs { + cluster-id = <0>; + min-volt = <950000>; /* uV */ + min-freq = <216000>; /* KHz */ + leakage-adjust-volt = < + /* mA mA uV */ + 0 254 0 + >; + nvmem-cells = <&cpu_leakage>; + nvmem-cell-names = "cpu_leakage"; + }; + cluster1-avs { + cluster-id = <1>; + min-volt = <950000>; /* uV */ + min-freq = <216000>; /* KHz */ + leakage-adjust-volt = < + /* mA mA uV */ + 0 254 0 + >; + nvmem-cells = <&cpu_leakage>; + nvmem-cell-names = "cpu_leakage"; }; }; @@ -213,6 +428,8 @@ #dma-cells = <1>; clocks = <&cru ACLK_DMAC_PERI>; clock-names = "apb_pclk"; + arm,pl330-broken-no-flushp; + peripherals-req-type-burst; }; dmac_bus: dma-controller@ff600000 { @@ -223,6 +440,8 @@ #dma-cells = <1>; clocks = <&cru ACLK_DMAC_BUS>; clock-names = "apb_pclk"; + arm,pl330-broken-no-flushp; + peripherals-req-type-burst; }; }; @@ -250,12 +469,13 @@ #clock-cells = <0>; }; - sdmmc: rksdmmc@ff0c0000 { + sdmmc: dwmmc@ff0c0000 { compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xff0c0000 0x0 0x4000>; clock-freq-min-max = <400000 150000000>; - clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; - clock-names = "biu", "ciu"; + clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, + <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; fifo-depth = <0x100>; interrupts = ; status = "disabled"; @@ -273,12 +493,13 @@ status = "disabled"; }; - emmc: rksdmmc@ff0f0000 { + emmc: dwmmc@ff0f0000 { compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xff0f0000 0x0 0x4000>; clock-freq-min-max = <400000 150000000>; - clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>; - clock-names = "biu", "ciu"; + clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, + <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; fifo-depth = <0x100>; interrupts = ; status = "disabled"; @@ -291,6 +512,8 @@ #io-channel-cells = <1>; clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; clock-names = "saradc", "apb_pclk"; + resets = <&cru SRST_SARADC>; + reset-names = "saradc-apb"; status = "disabled"; }; @@ -333,16 +556,29 @@ status = "disabled"; }; - i2c1: i2c@ff140000 { + i2c0: i2c@ff650000 { + compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; + reg = <0x0 0xff650000 0x0 0x1000>; + clocks = <&cru PCLK_I2C0>; + clock-names = "i2c"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@ff140000 { compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; reg = <0x0 0xff140000 0x0 0x1000>; interrupts = ; #address-cells = <1>; #size-cells = <0>; clock-names = "i2c"; - clocks = <&cru PCLK_I2C1>; + clocks = <&cru PCLK_I2C2>; pinctrl-names = "default"; - pinctrl-0 = <&i2c1_xfer>; + pinctrl-0 = <&i2c2_xfer>; status = "disabled"; }; @@ -433,6 +669,77 @@ status = "disabled"; }; + thermal_zones: thermal-zones { + soc_thermal: soc-thermal { + polling-delay-passive = <200>; /* milliseconds */ + polling-delay = <200>; /* milliseconds */ + sustainable-power = <600>; /* milliwatts */ + + thermal-sensors = <&tsadc 0>; + trips { + threshold: trip-point@0 { + temperature = <70000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + target: trip-point@1 { + temperature = <80000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + soc_crit: soc-crit { + temperature = <95000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&target>; + cooling-device = + <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <1024>; + }; + map1 { + trip = <&target>; + cooling-device = + <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <1024>; + }; + map2 { + trip = <&target>; + cooling-device = + <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <1024>; + }; + }; + }; + + gpu_thermal: gpu-thermal { + polling-delay-passive = <200>; /* milliseconds */ + polling-delay = <200>; /* milliseconds */ + thermal-sensors = <&tsadc 1>; + }; + }; + + tsadc: tsadc@ff280000 { + compatible = "rockchip,rk3368-tsadc-legacy"; + reg = <0x0 0xff280000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; + clock-names = "tsadc", "apb_pclk"; + clock-frequency = <32768>; + resets = <&cru SRST_TSADC>; + reset-names = "tsadc-apb"; + nvmem-cells = <&temp_adjust>; + nvmem-cell-names = "temp_adjust"; + #thermal-sensor-cells = <1>; + hw-shut-temp = <95000>; + latency-bound = <50000>; + status = "disabled"; + }; + gmac: ethernet@ff290000 { compatible = "rockchip,rk3368-gmac"; reg = <0x0 0xff290000 0x0 0x10000>; @@ -450,12 +757,35 @@ status = "disabled"; }; + nandc0: nandc@ff400000 { + compatible = "rockchip,rk-nandc"; + reg = <0x0 0xff400000 0x0 0x4000>; + interrupts = ; + nandc_id = <0>; + clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>; + clock-names = "clk_nandc", "hclk_nandc"; + status = "disabled"; + }; + usb_host0_ehci: usb@ff500000 { compatible = "generic-ehci"; - reg = <0x0 0xff500000 0x0 0x100>; + reg = <0x0 0xff500000 0x0 0x20000>; interrupts = ; - clocks = <&cru HCLK_HOST0>; - clock-names = "usbhost"; + clocks = <&cru HCLK_HOST0>, <&u2phy>; + clock-names = "usbhost", "utmi"; + phys = <&u2phy_host>; + phy-names = "usb"; + status = "disabled"; + }; + + usb_host0_ohci: usb@ff520000 { + compatible = "generic-ohci"; + reg = <0x0 0xff520000 0x0 0x20000>; + interrupts = ; + clocks = <&cru HCLK_HOST0>, <&u2phy>; + clock-names = "usbhost", "utmi"; + phys = <&u2phy_host>; + phy-names = "usb"; status = "disabled"; }; @@ -479,29 +809,16 @@ reg = <0x0 0xff610000 0x0 0x400>; }; - i2c0: i2c@ff650000 { - compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; - reg = <0x0 0xff650000 0x0 0x1000>; - clocks = <&cru PCLK_I2C0>; - clock-names = "i2c"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_xfer>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@ff660000 { + i2c1: i2c@ff660000 { compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; reg = <0x0 0xff660000 0x0 0x1000>; interrupts = ; #address-cells = <1>; #size-cells = <0>; clock-names = "i2c"; - clocks = <&cru PCLK_I2C2>; + clocks = <&cru PCLK_I2C1>; pinctrl-names = "default"; - pinctrl-0 = <&i2c2_xfer>; + pinctrl-0 = <&i2c1_xfer>; status = "disabled"; }; @@ -560,14 +877,226 @@ status = "disabled"; }; + mbox: mbox@ff6b0000 { + compatible = "rockchip,rk3368-mailbox"; + reg = <0x0 0xff6b0000 0x0 0x1000>; + interrupts = , + , + , + ; + clocks = <&cru PCLK_MAILBOX>; + clock-names = "pclk_mailbox"; + #mbox-cells = <1>; + status = "disabled"; + }; + + mailbox: mailbox@ff6b0000 { + compatible = "rockchip,rk3368-mbox-legacy"; + reg = <0x0 0xff6b0000 0x0 0x1000>, + <0x0 0xff8cf000 0x0 0x1000>; /* the end 4k of sram */ + interrupts = , + , + , + ; + clocks = <&cru PCLK_MAILBOX>; + clock-names = "pclk_mailbox"; + #mbox-cells = <1>; + status = "disabled"; + }; + + mailbox_scpi: mailbox-scpi { + compatible = "rockchip,rk3368-scpi-legacy"; + mboxes = <&mailbox 0>, <&mailbox 1>, <&mailbox 2>; + chan-nums = <3>; + status = "disabled"; + }; + + qos_iep: qos@ffad0000 { + compatible = "syscon"; + reg = <0x0 0xffad0000 0x0 0x20>; + }; + + qos_isp_r0: qos@ffad0080 { + compatible = "syscon"; + reg = <0x0 0xffad0080 0x0 0x20>; + }; + + qos_isp_r1: qos@ffad0100 { + compatible = "syscon"; + reg = <0x0 0xffad0100 0x0 0x20>; + }; + + qos_isp_w0: qos@ffad0180 { + compatible = "syscon"; + reg = <0x0 0xffad0180 0x0 0x20>; + }; + + qos_isp_w1: qos@ffad0200 { + compatible = "syscon"; + reg = <0x0 0xffad0200 0x0 0x20>; + }; + + qos_vip: qos@ffad0280 { + compatible = "syscon"; + reg = <0x0 0xffad0280 0x0 0x20>; + }; + + qos_vop: qos@ffad0300 { + compatible = "syscon"; + reg = <0x0 0xffad0300 0x0 0x20>; + }; + + qos_rga_r: qos@ffad0380 { + compatible = "syscon"; + reg = <0x0 0xffad0380 0x0 0x20>; + }; + + qos_rga_w: qos@ffad0400 { + compatible = "syscon"; + reg = <0x0 0xffad0400 0x0 0x20>; + }; + + qos_hevc_r: qos@ffae0000 { + compatible = "syscon"; + reg = <0x0 0xffae0000 0x0 0x20>; + }; + + qos_vpu_r: qos@ffae0100 { + compatible = "syscon"; + reg = <0x0 0xffae0100 0x0 0x20>; + }; + + qos_vpu_w: qos@ffae0180 { + compatible = "syscon"; + reg = <0x0 0xffae0180 0x0 0x20>; + }; + + qos_gpu: qos@ffaf0000 { + compatible = "syscon"; + reg = <0x0 0xffaf0000 0x0 0x20>; + }; + pmu: power-management@ff730000 { - compatible = "rockchip,rk3368-pmu", "syscon"; + compatible = "rockchip,rk3368-pmu", "syscon", "simple-mfd"; reg = <0x0 0xff730000 0x0 0x1000>; + + power: power-controller { + compatible = "rockchip,rk3368-power-controller"; + #power-domain-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + /* + * Note: Although SCLK_* are the working clocks + * of device without including on the NOC, needed for + * synchronous reset. + * + * The clocks on the which NOC: + * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU. + * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU. + * ACLK_RGA is on ACLK_RGA_NIU. + * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU. + * + * Which clock are device clocks: + * clocks devices + * *_IEP IEP:Image Enhancement Processor + * *_ISP ISP:Image Signal Processing + * *_VIP VIP:Video Input Processor + * *_VOP* VOP:Visual Output Processor + * *_RGA RGA + * *_EDP* EDP + * *_DPHY* LVDS + * *_HDMI HDMI + * *_MIPI_* MIPI + */ + pd_vio { + reg = ; + clocks = <&cru ACLK_IEP>, + <&cru ACLK_ISP>, + <&cru ACLK_VIP>, + <&cru ACLK_RGA>, + <&cru ACLK_VOP>, + <&cru ACLK_VOP_IEP>, + <&cru DCLK_VOP>, + <&cru HCLK_IEP>, + <&cru HCLK_ISP>, + <&cru HCLK_RGA>, + <&cru HCLK_VIP>, + <&cru HCLK_VOP>, + <&cru HCLK_VIO_HDCPMMU>, + <&cru PCLK_EDP_CTRL>, + <&cru PCLK_HDMI_CTRL>, + <&cru PCLK_HDCP>, + <&cru PCLK_ISP>, + <&cru PCLK_VIP>, + <&cru PCLK_DPHYRX>, + <&cru PCLK_DPHYTX0>, + <&cru PCLK_MIPI_CSI>, + <&cru PCLK_MIPI_DSI0>, + <&cru SCLK_VOP0_PWM>, + <&cru SCLK_EDP_24M>, + <&cru SCLK_EDP>, + <&cru SCLK_HDCP>, + <&cru SCLK_ISP>, + <&cru SCLK_RGA>, + <&cru SCLK_HDMI_CEC>, + <&cru SCLK_HDMI_HDCP>; + pm_qos = <&qos_iep>, + <&qos_isp_r0>, + <&qos_isp_r1>, + <&qos_isp_w0>, + <&qos_isp_w1>, + <&qos_vip>, + <&qos_vop>, + <&qos_rga_r>, + <&qos_rga_w>; + }; + /* + * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC + * (video endecoder & decoder) clocks that on the + * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC). + */ + pd_video { + reg = ; + clocks = <&cru ACLK_VIDEO>, + <&cru HCLK_VIDEO>, + <&cru SCLK_HEVC_CABAC>, + <&cru SCLK_HEVC_CORE>; + pm_qos = <&qos_hevc_r>, + <&qos_vpu_r>, + <&qos_vpu_w>; + }; + /* + * Note: ACLK_GPU is the GPU clock, + * and on the ACLK_GPU_NIU (NOC). + */ + pd_gpu_1 { + reg = ; + clocks = <&cru ACLK_GPU_CFG>, + <&cru ACLK_GPU_MEM>, + <&cru SCLK_GPU_CORE>; + pm_qos = <&qos_gpu>; + }; + }; }; pmugrf: syscon@ff738000 { - compatible = "rockchip,rk3368-pmugrf", "syscon"; + compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd"; reg = <0x0 0xff738000 0x0 0x1000>; + + pmu_io_domains: io-domains { + compatible = "rockchip,rk3368-pmu-io-voltage-domain"; + status = "disabled"; + }; + + reboot-mode { + compatible = "syscon-reboot-mode"; + offset = <0x200>; + mode-normal = ; + mode-recovery = ; + mode-bootloader = ; + mode-loader = ; + }; }; cru: clock-controller@ff760000 { @@ -576,11 +1105,59 @@ rockchip,grf = <&grf>; #clock-cells = <1>; #reset-cells = <1>; + assigned-clocks = + <&cru PLL_GPLL>, <&cru PLL_CPLL>, + <&cru ACLK_BUS>, <&cru ACLK_PERI>, + <&cru HCLK_BUS>, <&cru HCLK_PERI>, + <&cru PCLK_BUS>, <&cru PCLK_PERI>, + <&cru ACLK_CCI_PRE>; + assigned-clock-rates = + <576000000>, <400000000>, + <300000000>, <300000000>, + <150000000>, <150000000>, + <75000000>, <75000000>, + <576000000>; }; grf: syscon@ff770000 { - compatible = "rockchip,rk3368-grf", "syscon"; + compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd"; reg = <0x0 0xff770000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + edp_phy: edp-phy { + compatible = "rockchip,rk3368-dp-phy"; + clocks = <&cru SCLK_EDP_24M>; + clock-names = "24m"; + resets = <&cru SRST_EDP_24M>; + reset-names = "edp_24m"; + #phy-cells = <0>; + status = "disabled"; + }; + + io_domains: io-domains { + compatible = "rockchip,rk3368-io-voltage-domain"; + status = "disabled"; + }; + + u2phy: usb2-phy@700 { + compatible = "rockchip,rk3368-usb2phy"; + reg = <0x700 0x2c>; + clocks = <&cru SCLK_OTGPHY0>; + clock-names = "phyclk"; + #clock-cells = <0>; + clock-output-names = "usbotg_out"; + assigned-clocks = <&cru SCLK_USBPHY480M>; + assigned-clock-parents = <&u2phy>; + status = "disabled"; + + u2phy_host: host-port { + #phy-cells = <0>; + interrupts = ; + interrupt-names = "linestate"; + status = "disabled"; + }; + }; }; wdt: watchdog@ff800000 { @@ -591,30 +1168,20 @@ status = "disabled"; }; - gic: interrupt-controller@ffb71000 { - compatible = "arm,gic-400"; - interrupt-controller; - #interrupt-cells = <3>; - #address-cells = <0>; - - reg = <0x0 0xffb71000 0x0 0x1000>, - <0x0 0xffb72000 0x0 0x1000>, - <0x0 0xffb74000 0x0 0x2000>, - <0x0 0xffb76000 0x0 0x2000>; - interrupts = ; + timer@ff810000 { + compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer"; + reg = <0x0 0xff810000 0x0 0x20>; + interrupts = ; }; i2s_2ch: i2s-2ch@ff890000 { compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s"; - reg = <0x0 0xff898000 0x0 0x1000>; + reg = <0x0 0xff890000 0x0 0x1000>; interrupts = ; - #address-cells = <2>; - #size-cells = <0>; dmas = <&dmac_bus 6>, <&dmac_bus 7>; dma-names = "tx", "rx"; - clock-names = "i2s_hclk", "i2s_clk"; - clocks = <&cru HCLK_I2S_2CH>, <&cru SCLK_I2S_2CH>; + clock-names = "i2s_clk", "i2s_hclk"; + clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>; status = "disabled"; }; @@ -622,17 +1189,359 @@ compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s"; reg = <0x0 0xff898000 0x0 0x1000>; interrupts = ; - #address-cells = <1>; - #size-cells = <0>; dmas = <&dmac_bus 0>, <&dmac_bus 1>; dma-names = "tx", "rx"; - clock-names = "i2s_hclk", "i2s_clk"; - clocks = <&cru HCLK_I2S_8CH>, <&cru SCLK_I2S_8CH>; + clock-names = "i2s_clk", "i2s_hclk"; + clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>; pinctrl-names = "default"; pinctrl-0 = <&i2s_8ch_bus>; status = "disabled"; }; + iep: iep@ff900000 { + compatible = "rockchip,iep"; + iommu_enabled = <1>; + iommus = <&iep_mmu>; + reg = <0x0 0xff900000 0x0 0x800>; + interrupts = ; + clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; + clock-names = "aclk_iep", "hclk_iep"; + power-domains = <&power RK3368_PD_VIO>; + allocator = <1>; + version = <2>; + status = "disabled"; + }; + + iep_mmu: iommu@ff900800 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff900800 0x0 0x100>; + interrupts = ; + interrupt-names = "iep_mmu"; + power-domains = <&power RK3368_PD_VIO>; + #iommu-cells = <0>; + status = "disabled"; + }; + + isp: isp@ff910000 { + compatible = "rockchip,rk3368-isp", "rockchip,isp"; + reg = <0x0 0xff910000 0x0 0x4000>; + interrupts = ; + power-domains = <&power RK3368_PD_VIO>; + clocks = + <&cru ACLK_RGA>, <&cru HCLK_ISP>, <&cru SCLK_ISP>, + <&cru SCLK_ISP>, <&cru PCLK_ISP>, <&cru SCLK_VIP_OUT>, + <&cru SCLK_VIP_OUT>, <&cru PCLK_MIPI_CSI>, + <&cru PCLK_DPHYRX>, <&cru ACLK_VIO0_NOC>; + clock-names = + "aclk_isp", "hclk_isp", "clk_isp", + "clk_isp_jpe", "pclkin_isp", "clk_cif_out", + "clk_cif_pll", "hclk_mipiphy1", + "pclk_dphyrx", "clk_vio0_noc"; + + pinctrl-names = + "default", "isp_dvp8bit2", "isp_dvp10bit", + "isp_dvp12bit", "isp_dvp8bit0", "isp_dvp8bit4", + "isp_mipi_fl", "isp_mipi_fl_prefl", + "isp_flash_as_gpio", "isp_flash_as_trigger_out"; + pinctrl-0 = <&cif_clkout>; + pinctrl-1 = <&cif_clkout &isp_dvp_d2d9>; + pinctrl-2 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1>; + pinctrl-3 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>; + pinctrl-4 = <&cif_clkout &isp_dvp_d0d7>; + pinctrl-5 = <&cif_clkout &isp_dvp_d4d11>; + pinctrl-6 = <&cif_clkout>; + pinctrl-7 = <&cif_clkout &isp_prelight>; + pinctrl-8 = <&isp_flash_trigger_as_gpio>; + pinctrl-9 = <&isp_flash_trigger>; + rockchip,isp,mipiphy = <2>; + rockchip,isp,cifphy = <1>; + rockchip,isp,mipiphy1,reg = <0xff964000 0x4000>; + rockchip,isp,csiphy,reg = <0xff96C000 0x4000>; + rockchip,grf = <&grf>; + rockchip,cru = <&cru>; + rockchip,gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>; + rockchip,isp,iommu-enable = <1>; + iommus = <&isp_mmu>; + status = "disabled"; + }; + + isp_mmu: iommu@ff914000 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff914000 0x0 0x100>, + <0x0 0xff915000 0x0 0x100>; + interrupts = ; + interrupt-names = "isp_mmu"; + clocks = <&cru ACLK_RGA>, <&cru HCLK_ISP>; + clock-names = "aclk", "hclk"; + rk_iommu,disable_reset_quirk; + #iommu-cells = <0>; + power-domains = <&power RK3368_PD_VIO>; + status = "disabled"; + }; + + vop: vop@ff930000 { + compatible = "rockchip,rk3368-vop"; + reg = <0x0 0xff930000 0x0 0x2fc>; + interrupts = ; + clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>; + clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; + assigned-clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; + assigned-clock-rates = <400000000>, <200000000>; + resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>; + reset-names = "axi", "ahb", "dclk"; + power-domains = <&power RK3368_PD_VIO>; + iommus = <&vop_mmu>; + status = "disabled"; + + vop_out: port { + #address-cells = <1>; + #size-cells = <0>; + + vop_out_mipi: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_in_vop>; + }; + + vop_out_edp: endpoint@1 { + reg = <1>; + remote-endpoint = <&edp_in_vop>; + }; + }; + }; + + display_subsystem: display-subsystem { + compatible = "rockchip,display-subsystem"; + ports = <&vop_out>; + status = "disabled"; + }; + + vop_mmu: iommu@ff930300 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff930300 0x0 0x100>; + interrupts = ; + interrupt-names = "vop_mmu"; + clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; + clock-names = "aclk", "hclk"; + power-domains = <&power RK3368_PD_VIO>; + #iommu-cells = <0>; + status = "disabled"; + }; + + mipi_dsi_host: mipi-dsi-host@ff960000 { + compatible = "rockchip,rk3368-mipi-dsi"; + reg = <0x0 0xff960000 0x0 0x4000>; + interrupts = ; + clocks = <&cru PCLK_MIPI_DSI0>; + clock-names = "pclk"; + resets = <&cru SRST_MIPIDSI0>; + reset-names = "apb"; + phys = <&mipi_dphy>; + phy-names = "mipi_dphy"; + rockchip,grf = <&grf>; + power-domains = <&power RK3368_PD_VIO>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + ports { + port { + mipi_in_vop: endpoint { + remote-endpoint = <&vop_out_mipi>; + }; + }; + }; + }; + + mipi_dphy: mipi-dphy@ff968000 { + compatible = "rockchip,rk3368-mipi-dphy"; + reg = <0x0 0xff968000 0x0 0x4000>; + #phy-cells = <0>; + clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX0>; + clock-names = "ref", "pclk"; + resets = <&cru SRST_MIPIDPHYTX>; + reset-names = "apb"; + status = "disabled"; + }; + + edp: edp@ff970000 { + compatible = "rockchip,rk3368-edp"; + reg = <0x0 0xff970000 0x0 0x8000>; + interrupts = ; + clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>; + clock-names = "dp", "pclk"; + resets = <&cru SRST_EDP>; + reset-names = "dp"; + power-domains = <&power RK3368_PD_VIO>; + rockchip,grf = <&grf>; + phys = <&edp_phy>; + phy-names = "dp"; + pinctrl-names = "default"; + pinctrl-0 = <&edp_hpd>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + edp_in: port@0 { + reg = <0>; + + edp_in_vop: endpoint { + remote-endpoint = <&vop_out_edp>; + }; + }; + }; + }; + + hevc_mmu: iommu@ff9a0440 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff9a0440 0x0 0x40>, + <0x0 0xff9a0480 0x0 0x40>; + interrupts = ; + interrupt-names = "hevc_mmu"; + clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>; + clock-names = "aclk", "hclk"; + power-domains = <&power RK3368_PD_VIDEO>; + #iommu-cells = <0>; + status = "disabled"; + }; + + vpu_mmu: iommu@ff9a0800 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff9a0800 0x0 0x100>; + interrupts = , + ; + interrupt-names = "vepu_mmu", "vdpu_mmu"; + clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>; + clock-names = "aclk", "hclk"; + power-domains = <&power RK3368_PD_VIDEO>; + #iommu-cells = <0>; + status = "disabled"; + }; + + vpu: vpu_service { + compatible = "rockchip,vpu_sub"; + iommu_enabled = <1>; + iommus = <&vpu_mmu>; + interrupts = , + ; + interrupt-names = "irq_enc","irq_dec"; + dev_mode = <0>; + name = "vpu_service"; + allocator = <1>; + }; + + hevc: hevc_service { + compatible = "rockchip,hevc_sub"; + iommu_enabled = <1>; + iommus = <&hevc_mmu>; + interrupts = ; + interrupt-names = "irq_dec"; + dev_mode = <1>; + name = "hevc_service"; + allocator = <1>; + }; + + vpu_combo: vpu_combo@ff9a0000 { + compatible = "rockchip,vpu_combo"; + reg = <0x0 0xff9a0000 0x0 0x440>; + rockchip,grf = <&grf>; + subcnt = <2>; + rockchip,sub = <&vpu>, <&hevc>; + clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>, + <&cru SCLK_HEVC_CORE>, <&cru SCLK_HEVC_CABAC>; + clock-names = "aclk_vcodec", "hclk_vcodec", + "clk_core", "clk_cabac"; + resets = <&cru SRST_VIDEO_AXI>, <&cru SRST_VIDEO_AHB>, + <&cru SRST_VIDEO>; + reset-names = "video_a", "video_h", "video"; + mode_bit = <12>; + mode_ctrl = <0x418>; + name = "vpu_combo"; + power-domains = <&power RK3368_PD_VIDEO>; + status = "disabled"; + }; + + gic: interrupt-controller@ffb71000 { + compatible = "arm,gic-400"; + interrupt-controller; + #interrupt-cells = <3>; + #address-cells = <0>; + + reg = <0x0 0xffb71000 0x0 0x1000>, + <0x0 0xffb72000 0x0 0x2000>, + <0x0 0xffb74000 0x0 0x2000>, + <0x0 0xffb76000 0x0 0x2000>; + interrupts = ; + }; + + gpu: rogue-g6110@ffa30000 { + compatible = "arm,rogue-G6110", "arm,rk3368-gpu"; + reg = <0x0 0xffa30000 0x0 0x10000>; + clocks = + <&cru SCLK_GPU_CORE>, + <&cru ACLK_GPU_MEM>, + <&cru ACLK_GPU_CFG>; + clock-names = + "sclk_gpu_core", + "aclk_gpu_mem", + "aclk_gpu_cfg"; + interrupts = ; + interrupt-names = "rogue-g6110-irq"; + power-domains = <&power RK3368_PD_GPU_1>; + operating-points-v2 = <&gpu_opp_table>; + #cooling-cells = <2>; /* min followed by max */ + gpu_power_model: power_model { + compatible = "arm,mali-simple-power-model"; + voltage = <900>; + frequency = <500>; + static-power = <300>; + dynamic-power = <396>; + ts = <32000 4700 (-80) 2>; + thermal-zone = "gpu-thermal"; + }; + }; + + gpu_opp_table: gpu_opp_table { + compatible = "operating-points-v2"; + opp-shared; + + opp@200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <1100000>; + }; + opp@288000000 { + opp-hz = /bits/ 64 <288000000>; + opp-microvolt = <1100000>; + }; + opp@400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <1100000>; + }; + opp@576000000 { + opp-hz = /bits/ 64 <576000000>; + opp-microvolt = <1200000>; + }; + }; + + efuse: efuse@ffb00000 { + compatible = "rockchip,rk3368-efuse"; + reg = <0x0 0xffb00000 0x0 0x20>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cru PCLK_EFUSE256>; + clock-names = "pclk_efuse"; + + /* Data cells */ + cpu_leakage: cpu-leakage@17 { + reg = <0x17 0x1>; + }; + temp_adjust: temp-adjust@1f { + reg = <0x1f 0x1>; + }; + }; + pinctrl: pinctrl { compatible = "rockchip,rk3368-pinctrl"; rockchip,grf = <&grf>; @@ -710,6 +1619,12 @@ drive-strength = <12>; }; + edp { + edp_hpd: edp-hpd { + rockchip,pins = <2 23 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + emmc { emmc_clk: emmc-clk { rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; @@ -835,6 +1750,28 @@ }; }; + pwm0 { + pwm0_pin: pwm0-pin { + rockchip,pins = <3 8 RK_FUNC_2 &pcfg_pull_none>; + }; + + vop_pwm_pin: vop-pwm { + rockchip,pins = <3 8 RK_FUNC_3 &pcfg_pull_none>; + }; + }; + + pwm1 { + pwm1_pin: pwm1-pin { + rockchip,pins = <0 8 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + pwm3 { + pwm3_pin: pwm3-pin { + rockchip,pins = <3 29 RK_FUNC_3 &pcfg_pull_none>; + }; + }; + sdio0 { sdio0_bus1: sdio0-bus1 { rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>; @@ -885,7 +1822,7 @@ rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up>; }; - sdmmc_cd: sdmcc-cd { + sdmmc_cd: sdmmc-cd { rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up>; }; @@ -1020,191 +1957,80 @@ }; }; - pwm0 { - pwm0_pin: pwm0-pin { - rockchip,pins = <3 8 RK_FUNC_2 &pcfg_pull_none>; + isp { + cif_clkout: cif-clkout { + rockchip,pins = <1 11 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout }; - vop_pwm_pin: vop-pwm { - rockchip,pins = <3 8 RK_FUNC_3 &pcfg_pull_none>; + isp_dvp_d2d9: isp-dvp-d2d9 { + rockchip,pins = + <1 0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2 + <1 1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3 + <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4 + <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5 + <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6 + <1 5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7 + <1 6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8 + <1 7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9 + <1 8 RK_FUNC_1 &pcfg_pull_none>,//cif_sync + <1 9 RK_FUNC_1 &pcfg_pull_none>,//cif_href + <1 10 RK_FUNC_1 &pcfg_pull_none>,//cif_clkin + <1 11 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout + }; + + isp_dvp_d0d1: isp-dvp-d0d1 { + rockchip,pins = + <1 12 RK_FUNC_1 &pcfg_pull_none>,//cif_data0 + <1 13 RK_FUNC_1 &pcfg_pull_none>;//cif_data1 }; - }; - pwm1 { - pwm1_pin: pwm1-pin { - rockchip,pins = <0 8 RK_FUNC_2 &pcfg_pull_none>; + isp_dvp_d10d11:isp_d10d11 { + rockchip,pins = + <1 14 RK_FUNC_1 &pcfg_pull_none>,//cif_data10 + <1 15 RK_FUNC_1 &pcfg_pull_none>;//cif_data11 }; - }; - pwm3 { - pwm3_pin: pwm3-pin { - rockchip,pins = <3 29 RK_FUNC_3 &pcfg_pull_none>; + isp_dvp_d0d7: isp-dvp-d0d7 { + rockchip,pins = + <1 12 RK_FUNC_1 &pcfg_pull_none>,//cif_data0 + <1 13 RK_FUNC_1 &pcfg_pull_none>,//cif_data1 + <1 0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2 + <1 1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3 + <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4 + <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5 + <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6 + <1 5 RK_FUNC_1 &pcfg_pull_none>;//cif_data7 }; - }; - lcdc { - lcdc_lcdc: lcdc-lcdc { - rockchip,pins = - <0 14 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D10 - <0 15 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D11 - <0 16 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D12 - <0 17 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D13 - <0 18 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D14 - <0 18 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D15 - <0 20 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D16 - <0 21 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D17 - <0 22 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D18 - <0 23 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D19 - <0 24 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D20 - <0 25 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D21 - <0 26 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D22 - <0 27 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D23 - <0 31 RK_FUNC_1 &pcfg_pull_none>,//DCLK - <0 30 RK_FUNC_1 &pcfg_pull_none>,//DEN - <0 28 RK_FUNC_1 &pcfg_pull_none>,//HSYNC - <0 29 RK_FUNC_1 &pcfg_pull_none>;//VSYN - }; - - lcdc_gpio: lcdc-gpio { + isp_dvp_d4d11: isp-dvp-d4d11 { rockchip,pins = - <0 14 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D10 - <0 15 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D11 - <0 16 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D12 - <0 17 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D13 - <0 18 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D14 - <0 19 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D15 - <0 20 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D16 - <0 21 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D17 - <0 22 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D18 - <0 23 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D19 - <0 24 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D20 - <0 25 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D21 - <0 26 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D22 - <0 27 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D23 - <0 31 RK_FUNC_GPIO &pcfg_pull_none>,//DCLK - <0 30 RK_FUNC_GPIO &pcfg_pull_none>,//DEN - <0 28 RK_FUNC_GPIO &pcfg_pull_none>,//HSYNC - <0 29 RK_FUNC_GPIO &pcfg_pull_none>;//VSYN - }; - }; - }; - - fb: fb { - compatible = "rockchip,rk-fb"; - rockchip,disp-mode = ; - status = "disabled"; - }; - - rk_screen: screen { - compatible = "rockchip,screen"; - status = "disabled"; - }; - - lcdc: lcdc@ff930000 { - compatible = "rockchip,rk3368-lcdc"; - rockchip,grf = <&grf>; - rockchip,pmugrf = <&pmugrf>; - rockchip,cru = <&cru>; - rockchip,prop = ; - rockchip,pwr18 = <0>; - rockchip,iommu-enabled = <1>; - reg = <0x0 0xff930000 0x0 0x10000>; - interrupts = ; - clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>; - clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc"; - /*power-domains = <&power PD_VIO>;*/ - resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>; - reset-names = "axi", "ahb", "dclk"; - status = "disabled"; - }; - - lvds: lvds@ff968000 { - compatible = "rockchip,rk3368-lvds"; - rockchip,grf = <&grf>; - reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>; - reg-names = "mipi_lvds_phy", "mipi_lvds_ctl"; - clocks = <&cru PCLK_DPHYTX0>, <&cru PCLK_MIPI_DSI0>; - clock-names = "pclk_lvds", "pclk_lvds_ctl"; - /*power-domains = <&power PD_VIO>;*/ - status = "disabled"; - }; - - edp: edp@ff970000 { - compatible = "rockchip,rk32-edp"; - reg = <0x0 0xff970000 0x0 0x4000>; - rockchip,grf = <&grf>; - interrupts = ; - clocks = <&cru SCLK_EDP>, <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>; - clock-names = "clk_edp", "clk_edp_24m", "pclk_edp"; - /*power-domains = <&power PD_VIO>;*/ - resets = <&cru SRST_EDP_24M>, <&cru SRST_EDP>; - reset-names = "edp_24m", "edp_apb"; - status = "disabled"; - }; - - iep_mmu: iep-mmu { - dbgname = "iep"; - compatible = "rockchip,iep_mmu"; - reg = <0x0 0xff900800 0x0 0x100>; - interrupts = ; - interrupt-names = "iep_mmu"; - status = "disabled"; - }; - - vip_mmu: vip-mmu { - dbgname = "vip"; - compatible = "rockchip,vip_mmu"; - reg = <0x0 0xff950800 0x0 0x100>; - interrupts = ; - interrupt-names = "vip_mmu"; - status = "disabled"; - }; - - vopb_mmu: vopb-mmu { - dbgname = "vop"; - compatible = "rockchip,vopb_mmu"; - reg = <0x0 0xff930300 0x0 0x100>; - interrupts = ; - interrupt-names = "vop_mmu"; - status = "disabled"; - }; + <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4 + <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5 + <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6 + <1 5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7 + <1 6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8 + <1 7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9 + <1 14 RK_FUNC_1 &pcfg_pull_none>,//cif_data10 + <1 17 RK_FUNC_1 &pcfg_pull_none>;//cif_data11 + }; - isp_mmu: isp-mmu { - dbgname = "isp_mmu"; - compatible = "rockchip,isp_mmu"; - reg = <0x0 0xff914000 0x0 0x100>, - <0x0 0xff915000 0x0 0x100>; - interrupts = ; - interrupt-names = "isp_mmu"; - status = "disabled"; - }; + isp_shutter: isp-shutter { + rockchip,pins = + <3 19 RK_FUNC_2 &pcfg_pull_none>, //SHUTTEREN + <3 22 RK_FUNC_2 &pcfg_pull_none>;//SHUTTERTRIG + }; - hdcp_mmu: hdcp-mmu { - dbgname = "hdcp_mmu"; - compatible = "rockchip,hdcp_mmu"; - reg = <0x0 0xff940000 0x0 0x100>; - interrupts = ; - interrupt-names = "hdcp_mmu"; - status = "disabled"; - }; + isp_flash_trigger: isp-flash-trigger { + rockchip,pins = <3 20 RK_FUNC_2 &pcfg_pull_none>; //ISP_FLASHTRIGOU + }; - hevc_mmu: hevc-mmu { - dbgname = "hevc"; - compatible = "rockchip,hevc_mmu"; - reg = <0x0 0xff9a0440 0x0 0x40>, - <0x0 0xff9a0480 0x0 0x40>; - interrupts = ; - interrupt-names = "hevc_mmu"; - status = "disabled"; - }; + isp_prelight: isp-prelight { + rockchip,pins = <3 21 RK_FUNC_2 &pcfg_pull_none>;//ISP_PRELIGHTTRIG + }; - vpu_mmu: vpu-mmu { - dbgname = "vpu"; - compatible = "rockchip,vpu_mmu"; - reg = <0x0 0xff9a0800 0x0 0x100>; - interrupts = , - ; - interrupt-names = "vepu_mmu", "vdpu_mmu"; - status = "disabled"; + isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio { + rockchip,pins = <3 20 RK_FUNC_GPIO &pcfg_pull_none>;//ISP_FLASHTRIGOU + }; + }; }; };