X-Git-Url: http://plrg.eecs.uci.edu/git/?p=firefly-linux-kernel-4.4.55.git;a=blobdiff_plain;f=arch%2Farm64%2Fboot%2Fdts%2Frockchip%2Frk3366.dtsi;h=b9a371940240885d838ff84572d1afadba142b44;hp=f24c35621978db5d8487102967fa72ab9ba49e0b;hb=166ce57b57dd71e86bc70c7135dd8ef870dae126;hpb=d6ad7277b0aaf26cc1a99a05826b2acb69a3be7a

diff --git a/arch/arm64/boot/dts/rockchip/rk3366.dtsi b/arch/arm64/boot/dts/rockchip/rk3366.dtsi
index f24c35621978..b9a371940240 100644
--- a/arch/arm64/boot/dts/rockchip/rk3366.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3366.dtsi
@@ -46,6 +46,10 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/pinctrl/rockchip.h>
 #include <dt-bindings/display/rk_fb.h>
+#include <dt-bindings/display/mipi_dsi.h>
+#include <dt-bindings/power/rk3366-power.h>
+#include <dt-bindings/soc/rockchip,boot-mode.h>
+#include <dt-bindings/thermal/thermal.h>
 
 / {
 	compatible = "rockchip,rk3366";
@@ -76,6 +80,11 @@
 			compatible = "arm,cortex-a53","arm,armv8";
 			reg = <0x0 0x0>;
 			enable-method = "psci";
+			clocks = <&cru ARMCLK>;
+			operating-points-v2 = <&cpu0_opp_table>;
+			cpu-idle-states = <&cpu_sleep>;
+			#cooling-cells = <2>; /* min followed by max */
+			dynamic-power-coefficient = <166>;
 		};
 
 		cpu1: cpu@1 {
@@ -83,6 +92,8 @@
 			compatible = "arm,cortex-a53","arm,armv8";
 			reg = <0x0 0x1>;
 			enable-method = "psci";
+			operating-points-v2 = <&cpu0_opp_table>;
+			cpu-idle-states = <&cpu_sleep>;
 		};
 
 		cpu2: cpu@2 {
@@ -90,6 +101,8 @@
 			compatible = "arm,cortex-a53","arm,armv8";
 			reg = <0x0 0x2>;
 			enable-method = "psci";
+			operating-points-v2 = <&cpu0_opp_table>;
+			cpu-idle-states = <&cpu_sleep>;
 		};
 
 		cpu3: cpu@3 {
@@ -97,6 +110,66 @@
 			compatible = "arm,cortex-a53","arm,armv8";
 			reg = <0x0 0x3>;
 			enable-method = "psci";
+			operating-points-v2 = <&cpu0_opp_table>;
+			cpu-idle-states = <&cpu_sleep>;
+		};
+
+		idle-states {
+			entry-method = "psci";
+			cpu_sleep: cpu-sleep-0 {
+				compatible = "arm,idle-state";
+				local-timer-stop;
+				arm,psci-suspend-param = <0x0010000>;
+				entry-latency-us = <350>;
+				exit-latency-us = <600>;
+				min-residency-us = <1150>;
+			};
+		};
+	};
+
+	cpu0_opp_table: opp_table0 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp@408000000 {
+			opp-hz = /bits/ 64 <408000000>;
+			opp-microvolt = <950000>;
+			clock-latency-ns = <40000>;
+			opp-suspend;
+		};
+		opp@600000000 {
+			opp-hz = /bits/ 64 <600000000>;
+			opp-microvolt = <950000>;
+		};
+		opp@816000000 {
+			opp-hz = /bits/ 64 <816000000>;
+			opp-microvolt = <1000000>;
+		};
+		opp@1008000000 {
+			opp-hz = /bits/ 64 <1008000000>;
+			opp-microvolt = <1075000>;
+		};
+		opp@1200000000 {
+			opp-hz = /bits/ 64 <1200000000>;
+			opp-microvolt = <1175000>;
+		};
+		opp@1296000000 {
+			opp-hz = /bits/ 64 <1296000000>;
+			opp-microvolt = <1250000>;
+		};
+	};
+
+	cpu_avs: cpu-avs {
+		cluster0-avs {
+			cluster-id = <0>;
+			min-volt = <950000>; /* uV */
+			min-freq = <408000>; /* KHz */
+			leakage-adjust-volt = <
+			/*  mA        mA         uV */
+			    0         254        0
+			>;
+			nvmem-cells = <&cpu_leakage>;
+			nvmem-cell-names = "cpu_leakage";
 		};
 	};
 
@@ -107,16 +180,22 @@
 
 	timer {
 		compatible = "arm,armv8-timer";
-		interrupts = <
-				GIC_PPI 13
-			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
-				<GIC_PPI 14
-			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
-				<GIC_PPI 11
-			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
-				<GIC_PPI 10
-			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
-		clock-frequency = <24000000>;
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+	};
+
+	arm-pmu {
+		compatible = "arm,cortex-a53-pmu";
+		interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&cpu0>,
+				     <&cpu1>,
+				     <&cpu2>,
+				     <&cpu3>;
 	};
 
 	xin24m: xin24m {
@@ -186,6 +265,82 @@
 		status = "disabled";
 	};
 
+	scr: rkscr@ff1d0000 {
+		compatible = "rockchip-scr";
+		reg = <0x0 0xff1d0000 0x0 0x10000>;
+		interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&scr_io &scr_detect &scr_rst &scr_clk>;
+		clocks = <&cru PCLK_SIM>;
+		clock-names = "g_pclk_sim_card";
+		status = "disabled";
+	};
+
+	thermal-zones {
+		soc_thermal: soc-thermal {
+			polling-delay-passive = <100>; /* milliseconds */
+			polling-delay = <1000>; /* milliseconds */
+			sustainable-power = <1600>; /* milliwatts */
+
+			thermal-sensors = <&tsadc 0>;
+
+			trips {
+				threshold: trip-point@0 {
+					temperature = <70000>; /* millicelsius */
+					hysteresis = <2000>; /* millicelsius */
+					type = "passive";
+				};
+				target: trip-point@1 {
+					temperature = <85000>; /* millicelsius */
+					hysteresis = <2000>; /* millicelsius */
+					type = "passive";
+				};
+				soc_crit: soc-crit {
+					temperature = <95000>; /* millicelsius */
+					hysteresis = <2000>; /* millicelsius */
+					type = "critical";
+				};
+			};
+
+			cooling-maps {
+				map0 {
+					trip = <&target>;
+					cooling-device =
+						<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+				map1 {
+					trip = <&target>;
+					cooling-device =
+						<&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+		};
+
+		gpu_thermal: gpu-thermal {
+			polling-delay-passive = <100>; /* milliseconds */
+			polling-delay = <1000>; /* milliseconds */
+
+			thermal-sensors = <&tsadc 1>;
+		};
+	};
+
+	tsadc: tsadc@ff260000 {
+		compatible = "rockchip,rk3366-tsadc";
+		reg = <0x0 0xff260000 0x0 0x100>;
+		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
+		clock-names = "tsadc", "apb_pclk";
+		resets = <&cru SRST_TSADC>;
+		reset-names = "tsadc-apb";
+		pinctrl-names = "default";
+		pinctrl-0 = <&tsadc_gpio>;
+		#thermal-sensor-cells = <1>;
+		rockchip,hw-tshut-temp = <95000>;
+		status = "disabled";
+	};
+
 	sdmmc: rksdmmc@ff400000 {
 		compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
 		clock-freq-min-max = <400000 150000000>;
@@ -229,7 +384,7 @@
 		interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 		interrupt-names = "macirq";
 		clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
-			 <&cru SCLK_MAC_RX>, <&cru SCLK_MACREF>,
+			 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
 			 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
 			 <&cru PCLK_GMAC>;
 		clock-names = "stmmaceth", "mac_clk_rx",
@@ -334,6 +489,43 @@
 		status = "disabled";
 	};
 
+	usb_host0_ehci: usb@ff480000 {
+		compatible = "generic-ehci";
+		reg = <0x0 0xff480000 0x0 0x20000>;
+		interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru SCLK_USBPHY480M>, <&cru HCLK_HOST>;
+		clock-names = "usbphy_480m", "hclk_host0";
+		phys = <&u2phy_host>;
+		phy-names = "usb";
+		status = "disabled";
+	};
+
+	usb_host0_ohci: usb@ff4a0000 {
+		compatible = "generic-ohci";
+		reg = <0x0 0xff4a0000 0x0 0x20000>;
+		interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru SCLK_USBPHY480M>, <&cru HCLK_HOST>;
+		clock-names = "usbphy_480m", "hclk_host0";
+		phys = <&u2phy_host>;
+		phy-names = "usb";
+		status = "disabled";
+	};
+
+	usb_otg: usb@ff4c0000 {
+		compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
+			     "snps,dwc2";
+		reg = <0x0 0xff4c0000 0x0 0x40000>;
+		interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru HCLK_OTG>;
+		clock-names = "otg";
+		dr_mode = "otg";
+		g-np-tx-fifo-size = <16>;
+		g-rx-fifo-size = <275>;
+		g-tx-fifo-size = <256 128 128 64 64 32>;
+		g-use-dma;
+		status = "disabled";
+	};
+
 	i2c1: i2c@ff660000 {
 		compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 		reg = <0x0 0xff660000 0x0 0x1000>;
@@ -347,6 +539,29 @@
 		status = "disabled";
 	};
 
+	efuse: efuse@ff670000 {
+		compatible = "rockchip,rk3366-efuse";
+		reg = <0x0 0xff670000 0x0 0x20>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		clocks = <&cru PCLK_EFUSE_256>;
+		clock-names = "pclk_efuse";
+
+		/* Data cells */
+		cpu_leakage: cpu-leakage {
+			reg = <0x17 0x1>;
+		};
+		gpu_leakage: gpu-leakage {
+			reg = <0x18 0x1>;
+		};
+		logic_leakage: logic-leakage {
+			reg = <0x19 0x1>;
+		};
+		wafer_info: wafer-info {
+			reg = <0x1c 0x1>;
+		};
+	};
+
 	pwm0: pwm@ff680000 {
 		compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 		reg = <0x0 0xff680000 0x0 0x10>;
@@ -402,9 +617,129 @@
 		status = "disabled";
 	};
 
+	pmu: power-management@ff730000 {
+		compatible = "rockchip,rk3366-pmu", "syscon", "simple-mfd";
+		reg = <0x0 0xff730000 0x0 0x1000>;
+
+		power: power-controller {
+			status = "disabled";
+			compatible = "rockchip,rk3366-power-controller";
+			#power-domain-cells = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			/*
+			 * Note: Although SCLK_* are the working clocks
+			 * of device without including on the NOC, needed for
+			 * synchronous reset.
+			 *
+			 * The clocks on the which NOC:
+			 * ACLK_IEP/ACLK_VOP0 are on ACLK_VIO0_NIU.
+			 * ACLK_RGA/ACLK_VOP1 are on ACLK_RGA_NIU.
+			 * ACLK_ISP is on ACLK_ISP_NIU.
+			 * ACLK_HDCP is on ACLK_HDCP_NIU.
+			 * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
+			 *
+			 * Which clock are device clocks:
+			 *	clocks		devices
+			 *	*_IEP		IEP:Image Enhancement Processor
+			 *	*_ISP		ISP:Image Signal Processing
+			 *	*_VOP*		VOP:Visual Output Processor
+			 *	*_RGA		RGA
+			 *	*_DPHY*		LVDS
+			 *	*_HDMI		HDMI
+			 *	*_MIPI_*	MIPI
+			 */
+			pd_vio {
+				reg = <RK3366_PD_VIO>;
+				clocks = <&cru ACLK_IEP>,
+					 <&cru ACLK_ISP>,
+					 <&cru ACLK_RGA>,
+					 <&cru ACLK_HDCP>,
+					 <&cru ACLK_VOP_FULL>,
+					 <&cru ACLK_VOP_LITE>,
+					 <&cru ACLK_VOP_IEP>,
+					 <&cru DCLK_VOP_FULL>,
+					 <&cru DCLK_VOP_LITE>,
+					 <&cru HCLK_IEP>,
+					 <&cru HCLK_ISP>,
+					 <&cru HCLK_RGA>,
+					 <&cru HCLK_VOP_FULL>,
+					 <&cru HCLK_VOP_LITE>,
+					 <&cru HCLK_VIO_HDCPMMU>,
+					 <&cru PCLK_HDMI_CTRL>,
+					 <&cru PCLK_HDCP>,
+					 <&cru PCLK_MIPI_DSI0>,
+					 <&cru SCLK_VOP_FULL_PWM>,
+					 <&cru SCLK_HDCP>,
+					 <&cru SCLK_ISP>,
+					 <&cru SCLK_RGA>,
+					 <&cru SCLK_HDMI_CEC>,
+					 <&cru SCLK_HDMI_HDCP>;
+			};
+
+			/*
+			 * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
+			 * (video endecoder & decoder) clocks that on the
+			 * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
+			 */
+			pd_vpu {
+				reg = <RK3366_PD_VPU>;
+				clocks = <&cru ACLK_VIDEO>,
+					 <&cru HCLK_VIDEO>;
+			};
+
+			/*
+			 * Note: ACLK_RKVDEC/HCLK_RKVDEC are RKVDEC
+			 * (video decoder) clocks that on the
+			 * ACLK_RKVDEC_NIU and HCLK_RKVDEC_NIU (NOC).
+			 */
+			pd_rkvdec {
+				reg = <RK3366_PD_RKVDEC>;
+				clocks = <&cru ACLK_RKVDEC>,
+					 <&cru HCLK_RKVDEC>;
+			};
+
+			pd_video {
+				reg = <RK3366_PD_VIDEO>;
+				clocks = <&cru ACLK_VIDEO>,
+					 <&cru ACLK_RKVDEC>,
+					 <&cru HCLK_VIDEO>,
+					 <&cru HCLK_RKVDEC>,
+					 <&cru SCLK_HEVC_CABAC>,
+					 <&cru SCLK_HEVC_CORE>;
+			};
+
+			/*
+			 * Note: ACLK_GPU is the GPU clock,
+			 * and on the ACLK_GPU_NIU (NOC).
+			 */
+			pd_gpu {
+				reg = <RK3366_PD_GPU>;
+				clocks = <&cru ACLK_GPU>;
+			};
+		};
+	};
+
 	pmugrf: syscon@ff738000 {
-		compatible = "rockchip,rk3366-pmugrf", "syscon";
+		compatible = "rockchip,rk3366-pmugrf", "syscon", "simple-mfd";
 		reg = <0x0 0xff738000 0x0 0x1000>;
+
+		reboot-mode {
+			compatible = "syscon-reboot-mode";
+			offset = <0x200>;
+			mode-normal = <BOOT_NORMAL>;
+			mode-recovery = <BOOT_RECOVERY>;
+			mode-fastboot = <BOOT_FASTBOOT>;
+			mode-loader = <BOOT_BL_DOWNLOAD>;
+		};
+
+		pmu_pvtm: pmu-pvtm {
+			compatible = "rockchip,rk3366-pmu-pvtm";
+			clocks = <&cru SCLK_PVTM_PMU>;
+			clock-names = "pmu";
+			status = "disabled";
+		};
 	};
 
 	amba {
@@ -421,6 +756,7 @@
 			#dma-cells = <1>;
 			clocks = <&cru ACLK_DMAC_PERI>;
 			clock-names = "apb_pclk";
+			peripherals-req-type-burst;
 		};
 
 		dmac_bus: dma-controller@ff600000 {
@@ -431,6 +767,7 @@
 			#dma-cells = <1>;
 			clocks = <&cru ACLK_DMAC_BUS>;
 			clock-names = "apb_pclk";
+			peripherals-req-type-burst;
 		};
 	};
 
@@ -440,11 +777,110 @@
 		rockchip,grf = <&grf>;
 		#clock-cells = <1>;
 		#reset-cells = <1>;
+		assigned-clocks =
+			<&cru SCLK_WIFIDSP>, <&cru SCLK_32K>,
+			<&cru DCLK_VOP_FULL>, <&cru DCLK_VOP_LITE>,
+			<&cru SCLK_I2S_8CH_SRC>, <&cru SCLK_I2S_2CH_SRC>,
+			<&cru SCLK_SPDIF_8CH_SRC>,
+			<&cru PLL_CPLL>, <&cru PLL_GPLL>,
+			<&cru PLL_NPLL>, <&cru PLL_MPLL>,
+			<&cru PLL_WPLL>, <&cru PLL_BPLL>,
+			<&cru ACLK_VOP_FULL>, <&cru ACLK_VOP_LITE>,
+			<&cru HCLK_VOP_LITE>,<&cru HCLK_VOP_LITE>,
+			<&cru ACLK_BUS>, <&cru ACLK_PERI0>,
+			<&cru ACLK_PERI1>;
+		assigned-clock-rates =
+			<0>, <0>,
+			<0>, <0>,
+			<0>, <0>,
+			<0>,
+			<750000000>, <576000000>,
+			<594000000>, <594000000>,
+			<960000000>, <520000000>,
+			<375000000>, <288000000>,
+			<100000000>, <100000000>,
+			<288000000>, <288000000>,
+			<144000000>;
+		assigned-clock-parents =
+			<&cru SCLK_WIFI_WPLL>, <&cru SCLK_32K_INTR>,
+			<&cru SCLK_MPLL_SRC>, <&cru PLL_NPLL>,
+			<&cru PLL_GPLL>, <&cru PLL_GPLL>,
+			<&cru PLL_GPLL>;
 	};
 
 	grf: syscon@ff770000 {
-		compatible = "rockchip,rk3366-grf", "syscon";
+		compatible = "rockchip,rk3366-grf", "syscon", "simple-mfd";
 		reg = <0x0 0xff770000 0x0 0x1000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		u2phy: usb2-phy@700 {
+			compatible = "rockchip,rk3366-usb2phy";
+			reg = <0x700 0x2c>;
+			clocks = <&cru SCLK_OTG_PHY0>;
+			clock-names = "phyclk";
+			#clock-cells = <0>;
+			clock-output-names = "sclk_otgphy0_480m";
+
+			u2phy_host: host-port {
+				#phy-cells = <0>;
+				interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "linestate";
+				status = "okay";
+			};
+		};
+
+		pvtm: pvtm {
+			compatible = "rockchip,rk3366-pvtm";
+			clocks = <&cru SCLK_PVTM_CORE>, <&cru SCLK_PVTM_GPU>;
+			clock-names = "core", "gpu";
+			status = "disabled";
+		};
+	};
+
+	wdt: watchdog@ff800000 {
+		compatible = "snps,dw-wdt";
+		reg = <0x0 0xff800000 0x0 0x100>;
+		clocks = <&cru PCLK_WDT>;
+		interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+		status = "disabled";
+	};
+
+	spdif: spdif@ff880000 {
+		compatible = "rockchip,rk3366-spdif";
+		reg = <0x0 0xff880000 0x0 0x1000>;
+		interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+		dmas = <&dmac_bus 3>;
+		dma-names = "tx";
+		clock-names = "mclk", "hclk";
+		clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&spdif_bus>;
+		status = "disabled";
+	};
+
+	i2s_2ch: i2s-2ch@ff890000 {
+		compatible = "rockchip,rk3366-i2s", "rockchip,rk3066-i2s";
+		reg = <0x0 0xff890000 0x0 0x1000>;
+		interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+		dmas = <&dmac_bus 6>, <&dmac_bus 7>;
+		dma-names = "tx", "rx";
+		clock-names = "i2s_clk", "i2s_hclk";
+		clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>;
+		status = "disabled";
+	};
+
+	i2s_8ch: i2s-8ch@ff898000 {
+		compatible = "rockchip,rk3366-i2s", "rockchip,rk3066-i2s";
+		reg = <0x0 0xff898000 0x0 0x1000>;
+		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+		dmas = <&dmac_bus 0>, <&dmac_bus 1>;
+		dma-names = "tx", "rx";
+		clock-names = "i2s_clk", "i2s_hclk";
+		clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&i2s_8ch_bus>;
+		status = "disabled";
 	};
 
 	fb: fb {
@@ -481,6 +917,27 @@
 		status = "disabled";
 	};
 
+	iep: iep@ff900000 {
+		compatible = "rockchip,iep";
+		iommu_enabled = <1>;
+		reg = <0x0 0xff900000 0x0 0x800>;
+		interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
+		clock-names = "aclk_iep", "hclk_iep";
+		version = <2>;
+		status = "disabled";
+	};
+
+	rga: rga@ff920000 {
+		compatible = "rockchip,rga2";
+		dev_mode = <1>;
+		reg = <0x0 0xff920000 0x0 0x1000>;
+		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
+		clock-names = "aclk_rga", "hclk_rga", "clk_rga";
+		status = "disabled";
+	};
+
 	vop_big: vop@ff930000 {
 		compatible = "rockchip,rk3366-lcdc-big";
 		rockchip,grf = <&grf>;
@@ -505,8 +962,36 @@
 		status = "disabled";
 	};
 
+	iep_mmu: iep-mmu {
+		dbgname = "iep";
+		compatible = "rockchip,iep_mmu";
+		reg = <0x0 0xff900800 0x0 0x100>;
+		interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "iep_mmu";
+		status = "disabled";
+	};
+
+	vpu_mmu: vpu_mmu {
+		dbgname = "vpu";
+		compatible = "rockchip,vpu_mmu";
+		reg = <0x0 0xff9a0800 0x0 0x100>;
+		interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "vpu_mmu";
+		status = "disabled";
+	};
+
+	vdec_mmu: vdec_mmu {
+		dbgname = "vdec";
+		compatible = "rockchip,vdec_mmu";
+		reg = <0x0 0xff9b0480 0x0 0x40>,
+		      <0x0 0xff9b04c0 0x0 0x40>;
+		interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "vdec_mmu";
+		status = "disabled";
+	};
+
 	dsihost0: mipi@ff960000 {
-		compatible = "rockchip,rk3368-dsi";
+		compatible = "rockchip,rk3366-dsi";
 		rockchip,prop = <0>;
 		reg = <0x0 0xff960000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
 		reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
@@ -526,6 +1011,60 @@
 		status = "disabled";
 	};
 
+	hdmi: hdmi@ff980000 {
+		compatible = "rockchip,rk3366-hdmi";
+		reg = <0x0 0xff980000 0x0 0x20000>;
+		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru PCLK_HDMI_CTRL>,
+			 <&cru SCLK_HDMI_HDCP>,
+			 <&cru SCLK_HDMI_CEC>,
+			 <&cru DCLK_HDMIPHY>;
+		clock-names = "pclk_hdmi",
+			      "hdcp_clk_hdmi",
+			      "cec_clk_hdmi",
+			      "dclk_hdmi_phy";
+		resets = <&cru SRST_HDMI>;
+		reset-names = "hdmi";
+		pinctrl-names = "default", "gpio";
+		pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
+		pinctrl-1 = <&i2c5_gpio>;
+		status = "disabled";
+	};
+
+	vpu: vpu_service@ff9a0000 {
+		compatible = "rockchip,vpu_service";
+		rockchip,grf = <&grf>;
+		iommu_enabled = <1>;
+		reg = <0x0 0xff9a0000 0x0 0x800>;
+		interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "irq_dec", "irq_enc";
+		clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
+		clock-names = "aclk_vcodec", "hclk_vcodec";
+		resets = <&cru SRST_VIDEO_AHB>, <&cru SRST_VIDEO_AXI>;
+		reset-names = "video_h", "video_a";
+		name = "vpu_service";
+		dev_mode = <0>;
+		status = "disabled";
+	};
+
+	rkvdec: rkvdec@ff9b0000 {
+		compatible = "rockchip,rkvdec";
+		rockchip,grf = <&grf>;
+		iommu_enabled = <1>;
+		reg = <0x0 0xff9b0000 0x0 0x400>;
+		interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "irq_dec";
+		clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>,<&cru SCLK_HEVC_CABAC>,<&cru SCLK_HEVC_CORE>;
+		clock-names = "aclk_vcodec", "hclk_vcodec", "clk_cabac", "clk_core";
+		resets = <&cru SRST_RKVDEC_AHB>, <&cru SRST_VIDEO_AXI>;
+		reset-names = "video_h", "video_a";
+		dev_mode = <2>;
+		name = "rkvdec";
+		status = "disabled";
+	};
+
 	pinctrl: pinctrl {
 		compatible = "rockchip,rk3366-pinctrl";
 		rockchip,grf = <&grf>;
@@ -733,6 +1272,21 @@
 			};
 		};
 
+		hdmi_i2c {
+			hdmii2c_xfer: hdmii2c-xfer {
+				rockchip,pins =
+					<5 13 RK_FUNC_2 &pcfg_pull_none>,
+					<5 14 RK_FUNC_2 &pcfg_pull_none>;
+			};
+		};
+
+		hdmi_pin {
+			hdmi_cec: hdmi-cec {
+				rockchip,pins =
+					<5 12 RK_FUNC_1 &pcfg_pull_none>;
+			};
+		};
+
 		i2c0 {
 			i2c0_xfer: i2c0-xfer {
 				rockchip,pins =
@@ -744,8 +1298,8 @@
 		i2c1 {
 			i2c1_xfer: i2c1-xfer {
 				rockchip,pins =
-					<4 19 RK_FUNC_1 &pcfg_pull_none>,
-					<4 20 RK_FUNC_1 &pcfg_pull_none>;
+					<4 25 RK_FUNC_1 &pcfg_pull_none>,
+					<4 26 RK_FUNC_1 &pcfg_pull_none>;
 			};
 		};
 
@@ -755,6 +1309,12 @@
 					<5 15 RK_FUNC_2 &pcfg_pull_none>,
 					<5 16 RK_FUNC_2 &pcfg_pull_none>;
 			};
+
+			i2c2_gpio: i2c2-gpio {
+				rockchip,pins =
+					<5 15 RK_FUNC_GPIO &pcfg_pull_none>,
+					<5 16 RK_FUNC_GPIO &pcfg_pull_none>;
+			};
 		};
 
 		i2c3 {
@@ -771,6 +1331,12 @@
 					<5 8 RK_FUNC_1 &pcfg_pull_none>,
 					<5 9 RK_FUNC_1 &pcfg_pull_none>;
 			};
+
+			i2c4_gpio: i2c4-gpio {
+				rockchip,pins =
+					<5 8 RK_FUNC_GPIO &pcfg_pull_none>,
+					<5 9 RK_FUNC_GPIO &pcfg_pull_none>;
+			};
 		};
 
 		i2c5 {
@@ -779,6 +1345,11 @@
 					<5 13 RK_FUNC_1 &pcfg_pull_none>,
 					<5 14 RK_FUNC_1 &pcfg_pull_none>;
 			};
+			i2c5_gpio: i2c5-gpio {
+				rockchip,pins =
+					<5 13 RK_FUNC_GPIO &pcfg_pull_none>,
+					<5 14 RK_FUNC_GPIO &pcfg_pull_none>;
+			};
 		};
 
 		i2s {
@@ -796,6 +1367,13 @@
 			};
 		};
 
+		spdif {
+			spdif_bus: spdif-bus {
+				rockchip,pins =
+					<5 19 RK_FUNC_1 &pcfg_pull_none>;
+			};
+		};
+
 		spi0 {
 			spi0_clk: spi0-clk {
 				rockchip,pins =
@@ -822,19 +1400,41 @@
 		spi1 {
 			spi1_clk: spi1-clk {
 				rockchip,pins =
-					<2 4 RK_FUNC_2 &pcfg_pull_up>;
+					<2 4 RK_FUNC_3 &pcfg_pull_up>;
 			};
 			spi1_cs0: spi1-cs0 {
 				rockchip,pins =
-					<2 5 RK_FUNC_2 &pcfg_pull_up>;
+					<2 5 RK_FUNC_3 &pcfg_pull_up>;
+			};
+			spi1_tx: spi1-tx {
+				rockchip,pins =
+					<2 6 RK_FUNC_3 &pcfg_pull_up>;
 			};
 			spi1_rx: spi1-rx {
 				rockchip,pins =
-					<2 6 RK_FUNC_2 &pcfg_pull_up>;
+					<2 7 RK_FUNC_3 &pcfg_pull_up>;
 			};
-			spi1_tx: spi1-tx {
+		};
+
+		scr {
+			scr_clk: scr-clk {
+				rockchip,pins =
+					<5 8 RK_FUNC_2 &pcfg_pull_none>;
+			};
+
+			scr_io: scr-io {
+				rockchip,pins =
+					<5 9 RK_FUNC_2 &pcfg_pull_up>;
+			};
+
+			scr_rst: scr-rst {
 				rockchip,pins =
-					<2 7 RK_FUNC_2 &pcfg_pull_up>;
+					<5 10 RK_FUNC_1 &pcfg_pull_none>;
+			};
+
+			scr_detect: scr-detect {
+				rockchip,pins =
+					<5 11 RK_FUNC_1 &pcfg_pull_none>;
 			};
 		};
 
@@ -1004,17 +1604,19 @@
 					/* mac_rxd2 */
 					<2 6  RK_FUNC_1 &pcfg_pull_none>,
 					/* mac_txd3 */
-					<2 5  RK_FUNC_1 &pcfg_pull_none>,
+					<2 5  RK_FUNC_1 &pcfg_pull_none_12ma>,
 					/* mac_txd2 */
-					<2 4  RK_FUNC_1 &pcfg_pull_none>,
+					<2 4  RK_FUNC_1 &pcfg_pull_none_12ma>,
 					/* mac_rxd1 */
 					<2 3  RK_FUNC_1 &pcfg_pull_none>,
 					/* mac_rxd0 */
 					<2 2  RK_FUNC_1 &pcfg_pull_none>,
 					/* mac_txd1 */
-					<2 1  RK_FUNC_1 &pcfg_pull_none>,
+					<2 1  RK_FUNC_1 &pcfg_pull_none_12ma>,
 					/* mac_txd0 */
 					<2 0  RK_FUNC_1 &pcfg_pull_none>,
+					/* mac_txclkout */
+					<2 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
 					/* mac_crs */
 					/* <2 15 RK_FUNC_1 &pcfg_pull_none>, */
 					/* mac_rxclkin */
@@ -1022,7 +1624,7 @@
 					/* mac_mdio */
 					<2 13 RK_FUNC_1 &pcfg_pull_none>,
 					/* mac_txen */
-					<2 12 RK_FUNC_1 &pcfg_pull_none>,
+					<2 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
 					/* mac_clk */
 					<2 11 RK_FUNC_1 &pcfg_pull_none>,
 					/* mac_rxer */
@@ -1065,8 +1667,84 @@
 		eth_phy {
 			eth_phy_pwr: eth-phy-pwr {
 				rockchip,pins =
-					<0 24 RK_FUNC_GPIO &pcfg_pull_none>;
+					<0 25 RK_FUNC_GPIO &pcfg_pull_none>;
 			};
 		};
+
+		tsadc_pin {
+			tsadc_gpio: tsadc-gpio {
+				rockchip,pins =
+					<0 22 RK_FUNC_GPIO &pcfg_pull_none>;
+			};
+
+			tsadc_int: tsadc-int {
+				rockchip,pins =
+					<0 22 RK_FUNC_2 &pcfg_pull_none>;
+			};
+		};
+
+		usb2 {
+			host_vbus_drv: host-vbus-drv {
+				rockchip,pins =
+					<0 16 RK_FUNC_GPIO &pcfg_pull_none>;
+			};
+		};
+
+	};
+
+	gpu: gpu@ffa30000 {
+		compatible = "arm,malit764",
+			     "arm,malit76x",
+			     "arm,malit7xx",
+			     "arm,mali-midgard";
+
+		reg = <0x0 0xffa30000 0 0x10000>;
+
+		interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "GPU", "MMU", "JOB";
+
+		clocks = <&cru ACLK_GPU>;
+		clock-names = "clk_mali";
+		#cooling-cells = <2>; /* min followed by max */
+		operating-points-v2 = <&gpu_opp_table>;
+		status = "disabled";
+
+		power_model {
+			compatible = "arm,mali-simple-power-model";
+			voltage = <900>;
+			frequency = <500>;
+			static-power = <300>;
+			dynamic-power = <1780>;
+			ts = <32000 4700 (-80) 2>;
+			thermal-zone = "gpu-thermal";
+		};
+	};
+
+	gpu_opp_table: gpu_opp_table {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp@96000000 {
+			opp-hz = /bits/ 64 <96000000>;
+			opp-microvolt = <1100000>;
+		};
+		opp@192000000 {
+			opp-hz = /bits/ 64 <192000000>;
+			opp-microvolt = <1100000>;
+		};
+		opp@288000000 {
+			opp-hz = /bits/ 64 <288000000>;
+			opp-microvolt = <1100000>;
+		};
+		opp@375000000 {
+			opp-hz = /bits/ 64 <375000000>;
+			opp-microvolt = <1125000>;
+		};
+		opp@480000000 {
+			opp-hz = /bits/ 64 <480000000>;
+			opp-microvolt = <1200000>;
+		};
 	};
 };