X-Git-Url: http://plrg.eecs.uci.edu/git/?p=firefly-linux-kernel-4.4.55.git;a=blobdiff_plain;f=arch%2Farm64%2Fboot%2Fdts%2Frockchip%2Frk3366.dtsi;h=b9a371940240885d838ff84572d1afadba142b44;hp=75784150d756140cf5d005cca90460fa61395019;hb=d356b80cab42a2acb515bc08a1fcc99466627a83;hpb=460024031667bd7bac235a7824c2f630d52e5022 diff --git a/arch/arm64/boot/dts/rockchip/rk3366.dtsi b/arch/arm64/boot/dts/rockchip/rk3366.dtsi index 75784150d756..b9a371940240 100644 --- a/arch/arm64/boot/dts/rockchip/rk3366.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3366.dtsi @@ -48,7 +48,8 @@ #include #include #include -#include +#include +#include / { compatible = "rockchip,rk3366"; @@ -82,6 +83,8 @@ clocks = <&cru ARMCLK>; operating-points-v2 = <&cpu0_opp_table>; cpu-idle-states = <&cpu_sleep>; + #cooling-cells = <2>; /* min followed by max */ + dynamic-power-coefficient = <166>; }; cpu1: cpu@1 { @@ -128,34 +131,48 @@ compatible = "operating-points-v2"; opp-shared; - opp00 { + opp@408000000 { opp-hz = /bits/ 64 <408000000>; opp-microvolt = <950000>; clock-latency-ns = <40000>; opp-suspend; }; - opp01 { + opp@600000000 { opp-hz = /bits/ 64 <600000000>; opp-microvolt = <950000>; }; - opp02 { + opp@816000000 { opp-hz = /bits/ 64 <816000000>; opp-microvolt = <1000000>; }; - opp03 { + opp@1008000000 { opp-hz = /bits/ 64 <1008000000>; opp-microvolt = <1075000>; }; - opp04 { + opp@1200000000 { opp-hz = /bits/ 64 <1200000000>; opp-microvolt = <1175000>; }; - opp05 { + opp@1296000000 { opp-hz = /bits/ 64 <1296000000>; opp-microvolt = <1250000>; }; }; + cpu_avs: cpu-avs { + cluster0-avs { + cluster-id = <0>; + min-volt = <950000>; /* uV */ + min-freq = <408000>; /* KHz */ + leakage-adjust-volt = < + /* mA mA uV */ + 0 254 0 + >; + nvmem-cells = <&cpu_leakage>; + nvmem-cell-names = "cpu_leakage"; + }; + }; + psci { compatible = "arm,psci-1.0"; method = "smc"; @@ -261,6 +278,69 @@ status = "disabled"; }; + thermal-zones { + soc_thermal: soc-thermal { + polling-delay-passive = <100>; /* milliseconds */ + polling-delay = <1000>; /* milliseconds */ + sustainable-power = <1600>; /* milliwatts */ + + thermal-sensors = <&tsadc 0>; + + trips { + threshold: trip-point@0 { + temperature = <70000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + target: trip-point@1 { + temperature = <85000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + soc_crit: soc-crit { + temperature = <95000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&target>; + cooling-device = + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&target>; + cooling-device = + <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + gpu_thermal: gpu-thermal { + polling-delay-passive = <100>; /* milliseconds */ + polling-delay = <1000>; /* milliseconds */ + + thermal-sensors = <&tsadc 1>; + }; + }; + + tsadc: tsadc@ff260000 { + compatible = "rockchip,rk3366-tsadc"; + reg = <0x0 0xff260000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; + clock-names = "tsadc", "apb_pclk"; + resets = <&cru SRST_TSADC>; + reset-names = "tsadc-apb"; + pinctrl-names = "default"; + pinctrl-0 = <&tsadc_gpio>; + #thermal-sensor-cells = <1>; + rockchip,hw-tshut-temp = <95000>; + status = "disabled"; + }; + sdmmc: rksdmmc@ff400000 { compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc"; clock-freq-min-max = <400000 150000000>; @@ -409,32 +489,13 @@ status = "disabled"; }; - usbphy: phy { - compatible = "rockchip,rk336x-usb-phy"; - rockchip,grf = <&grf>; - #address-cells = <1>; - #size-cells = <0>; - - usbphy0: usb-phy0 { - #phy-cells = <0>; - #clock-cells = <0>; - reg = <0x700>; - }; - - usbphy1: usb-phy1 { - #phy-cells = <0>; - #clock-cells = <0>; - reg = <0x728>; - }; - }; - - usb_host0_echi: usb@ff480000 { + usb_host0_ehci: usb@ff480000 { compatible = "generic-ehci"; reg = <0x0 0xff480000 0x0 0x20000>; interrupts = ; - clocks = <&cru SCLK_OTG_PHY0>, <&cru HCLK_HOST>; - clock-names = "sclk_otgphy0", "hclk_host0"; - phys = <&usbphy1>; + clocks = <&cru SCLK_USBPHY480M>, <&cru HCLK_HOST>; + clock-names = "usbphy_480m", "hclk_host0"; + phys = <&u2phy_host>; phy-names = "usb"; status = "disabled"; }; @@ -443,8 +504,10 @@ compatible = "generic-ohci"; reg = <0x0 0xff4a0000 0x0 0x20000>; interrupts = ; - clocks = <&cru SCLK_OTG_PHY0>, <&cru HCLK_HOST>; - clock-names = "sclk_otgphy0", "hclk_host0"; + clocks = <&cru SCLK_USBPHY480M>, <&cru HCLK_HOST>; + clock-names = "usbphy_480m", "hclk_host0"; + phys = <&u2phy_host>; + phy-names = "usb"; status = "disabled"; }; @@ -476,6 +539,29 @@ status = "disabled"; }; + efuse: efuse@ff670000 { + compatible = "rockchip,rk3366-efuse"; + reg = <0x0 0xff670000 0x0 0x20>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cru PCLK_EFUSE_256>; + clock-names = "pclk_efuse"; + + /* Data cells */ + cpu_leakage: cpu-leakage { + reg = <0x17 0x1>; + }; + gpu_leakage: gpu-leakage { + reg = <0x18 0x1>; + }; + logic_leakage: logic-leakage { + reg = <0x19 0x1>; + }; + wafer_info: wafer-info { + reg = <0x1c 0x1>; + }; + }; + pwm0: pwm@ff680000 { compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm"; reg = <0x0 0xff680000 0x0 0x10>; @@ -645,7 +731,14 @@ mode-normal = ; mode-recovery = ; mode-fastboot = ; - mode-loader = ; + mode-loader = ; + }; + + pmu_pvtm: pmu-pvtm { + compatible = "rockchip,rk3366-pmu-pvtm"; + clocks = <&cru SCLK_PVTM_PMU>; + clock-names = "pmu"; + status = "disabled"; }; }; @@ -663,6 +756,7 @@ #dma-cells = <1>; clocks = <&cru ACLK_DMAC_PERI>; clock-names = "apb_pclk"; + peripherals-req-type-burst; }; dmac_bus: dma-controller@ff600000 { @@ -673,6 +767,7 @@ #dma-cells = <1>; clocks = <&cru ACLK_DMAC_BUS>; clock-names = "apb_pclk"; + peripherals-req-type-burst; }; }; @@ -685,6 +780,8 @@ assigned-clocks = <&cru SCLK_WIFIDSP>, <&cru SCLK_32K>, <&cru DCLK_VOP_FULL>, <&cru DCLK_VOP_LITE>, + <&cru SCLK_I2S_8CH_SRC>, <&cru SCLK_I2S_2CH_SRC>, + <&cru SCLK_SPDIF_8CH_SRC>, <&cru PLL_CPLL>, <&cru PLL_GPLL>, <&cru PLL_NPLL>, <&cru PLL_MPLL>, <&cru PLL_WPLL>, <&cru PLL_BPLL>, @@ -695,6 +792,8 @@ assigned-clock-rates = <0>, <0>, <0>, <0>, + <0>, <0>, + <0>, <750000000>, <576000000>, <594000000>, <594000000>, <960000000>, <520000000>, @@ -704,12 +803,39 @@ <144000000>; assigned-clock-parents = <&cru SCLK_WIFI_WPLL>, <&cru SCLK_32K_INTR>, - <&cru SCLK_MPLL_SRC>, <&cru PLL_NPLL>; + <&cru SCLK_MPLL_SRC>, <&cru PLL_NPLL>, + <&cru PLL_GPLL>, <&cru PLL_GPLL>, + <&cru PLL_GPLL>; }; grf: syscon@ff770000 { - compatible = "rockchip,rk3366-grf", "syscon"; + compatible = "rockchip,rk3366-grf", "syscon", "simple-mfd"; reg = <0x0 0xff770000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + u2phy: usb2-phy@700 { + compatible = "rockchip,rk3366-usb2phy"; + reg = <0x700 0x2c>; + clocks = <&cru SCLK_OTG_PHY0>; + clock-names = "phyclk"; + #clock-cells = <0>; + clock-output-names = "sclk_otgphy0_480m"; + + u2phy_host: host-port { + #phy-cells = <0>; + interrupts = ; + interrupt-names = "linestate"; + status = "okay"; + }; + }; + + pvtm: pvtm { + compatible = "rockchip,rk3366-pvtm"; + clocks = <&cru SCLK_PVTM_CORE>, <&cru SCLK_PVTM_GPU>; + clock-names = "core", "gpu"; + status = "disabled"; + }; }; wdt: watchdog@ff800000 { @@ -1544,6 +1670,26 @@ <0 25 RK_FUNC_GPIO &pcfg_pull_none>; }; }; + + tsadc_pin { + tsadc_gpio: tsadc-gpio { + rockchip,pins = + <0 22 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + tsadc_int: tsadc-int { + rockchip,pins = + <0 22 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + usb2 { + host_vbus_drv: host-vbus-drv { + rockchip,pins = + <0 16 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + }; gpu: gpu@ffa30000 { @@ -1561,31 +1707,42 @@ clocks = <&cru ACLK_GPU>; clock-names = "clk_mali"; + #cooling-cells = <2>; /* min followed by max */ operating-points-v2 = <&gpu_opp_table>; status = "disabled"; + + power_model { + compatible = "arm,mali-simple-power-model"; + voltage = <900>; + frequency = <500>; + static-power = <300>; + dynamic-power = <1780>; + ts = <32000 4700 (-80) 2>; + thermal-zone = "gpu-thermal"; + }; }; gpu_opp_table: gpu_opp_table { compatible = "operating-points-v2"; opp-shared; - opp00 { + opp@96000000 { opp-hz = /bits/ 64 <96000000>; opp-microvolt = <1100000>; }; - opp01 { + opp@192000000 { opp-hz = /bits/ 64 <192000000>; opp-microvolt = <1100000>; }; - opp02 { + opp@288000000 { opp-hz = /bits/ 64 <288000000>; opp-microvolt = <1100000>; }; - opp03 { + opp@375000000 { opp-hz = /bits/ 64 <375000000>; opp-microvolt = <1125000>; }; - opp04 { + opp@480000000 { opp-hz = /bits/ 64 <480000000>; opp-microvolt = <1200000>; };