X-Git-Url: http://plrg.eecs.uci.edu/git/?p=firefly-linux-kernel-4.4.55.git;a=blobdiff_plain;f=arch%2Farm%2Fboot%2Fdts%2Frk3288.dtsi;h=f7601f4f7bedd88d4a763e751c6366b719ccf435;hp=131759906f0a08880e6b2507abb173ca9571d487;hb=b913ab69f93fda49fba500188823593f140e724f;hpb=ef179e79e9b6f62da31fdc2a9662fd54b346b6f7 diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 131759906f0a..f7601f4f7bed 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -45,7 +45,8 @@ #include #include #include -#include +#include +#include #include "skeleton.dtsi" / { @@ -54,6 +55,7 @@ interrupt-parent = <&gic>; aliases { + ethernet0 = &gmac; i2c0 = &i2c0; i2c1 = &i2c1; i2c2 = &i2c2; @@ -94,23 +96,8 @@ compatible = "arm,cortex-a12"; reg = <0x500>; resets = <&cru SRST_CORE0>; - operating-points = < - /* KHz uV */ - 1608000 1350000 - 1512000 1300000 - 1416000 1200000 - 1200000 1100000 - 1008000 1050000 - 816000 1000000 - 696000 950000 - 600000 900000 - 408000 900000 - 312000 900000 - 216000 900000 - 126000 900000 - >; + operating-points-v2 = <&cpu0_opp_table>; #cooling-cells = <2>; /* min followed by max */ - clock-latency = <40000>; clocks = <&cru ARMCLK>; }; cpu1: cpu@501 { @@ -118,18 +105,97 @@ compatible = "arm,cortex-a12"; reg = <0x501>; resets = <&cru SRST_CORE1>; + operating-points-v2 = <&cpu0_opp_table>; }; cpu2: cpu@502 { device_type = "cpu"; compatible = "arm,cortex-a12"; reg = <0x502>; resets = <&cru SRST_CORE2>; + operating-points-v2 = <&cpu0_opp_table>; }; cpu3: cpu@503 { device_type = "cpu"; compatible = "arm,cortex-a12"; reg = <0x503>; resets = <&cru SRST_CORE3>; + operating-points-v2 = <&cpu0_opp_table>; + }; + }; + + cpu0_opp_table: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp@126000000 { + opp-hz = /bits/ 64 <126000000>; + opp-microvolt = <900000>; + clock-latency-ns = <40000>; + }; + opp@216000000 { + opp-hz = /bits/ 64 <216000000>; + opp-microvolt = <900000>; + clock-latency-ns = <40000>; + }; + opp@408000000 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <900000>; + clock-latency-ns = <40000>; + }; + opp@600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <900000>; + clock-latency-ns = <40000>; + }; + opp@696000000 { + opp-hz = /bits/ 64 <696000000>; + opp-microvolt = <950000>; + clock-latency-ns = <40000>; + }; + opp@816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + opp@1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <1050000>; + clock-latency-ns = <40000>; + }; + opp@1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <40000>; + }; + opp@1416000000 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <1200000>; + clock-latency-ns = <40000>; + }; + opp@1512000000 { + opp-hz = /bits/ 64 <1512000000>; + opp-microvolt = <1300000>; + clock-latency-ns = <40000>; + }; + opp@1608000000 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <1350000>; + clock-latency-ns = <40000>; + }; + }; + + cpu_avs: cpu-avs { + cluster0-avs { + cluster-id = <0>; + min-volt = <900000>; /* uV */ + min-freq = <126000>; /* KHz */ + leakage-adjust-volt = < + /* mA mA uV */ + 0 254 0 + >; + nvmem-cells = <&cpu_leakage>; + nvmem-cell-names = "cpu_leakage"; }; }; @@ -204,15 +270,6 @@ #clock-cells = <0>; }; - edp_phy: edp-phy { - compatible = "rockchip,rk3288-dp-phy"; - clocks = <&cru SCLK_EDP_24M>; - clock-names = "24m"; - rockchip,grf = <&grf>; - #phy-cells = <0>; - status = "disabled"; - }; - timer { compatible = "arm,armv7-timer"; arm,cpu-registers-not-fw-configured; @@ -292,6 +349,8 @@ #io-channel-cells = <1>; clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; clock-names = "saradc", "apb_pclk"; + resets = <&cru SRST_SARADC>; + reset-names = "saradc-apb"; status = "disabled"; }; @@ -340,6 +399,19 @@ status = "disabled"; }; + i2c0: i2c@ff650000 { + compatible = "rockchip,rk3288-i2c"; + reg = <0xff650000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "i2c"; + clocks = <&cru PCLK_I2C0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_xfer>; + status = "disabled"; + }; + i2c1: i2c@ff140000 { compatible = "rockchip,rk3288-i2c"; reg = <0xff140000 0x1000>; @@ -458,7 +530,78 @@ }; thermal-zones { - #include "rk3288-thermal.dtsi" + reserve_thermal: reserve_thermal { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&tsadc 0>; + }; + + cpu_thermal: cpu_thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&tsadc 1>; + + trips { + cpu_alert0: cpu_alert0 { + temperature = <70000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + cpu_alert1: cpu_alert1 { + temperature = <80000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + cpu_crit: cpu_crit { + temperature = <90000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = + <&cpu0 THERMAL_NO_LIMIT 6>; + }; + map1 { + trip = <&cpu_alert1>; + cooling-device = + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + gpu_thermal: gpu_thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&tsadc 2>; + + trips { + gpu_alert0: gpu_alert0 { + temperature = <80000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + gpu_crit: gpu_crit { + temperature = <90000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&gpu_alert0>; + cooling-device = + <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; }; tsadc: tsadc@ff280000 { @@ -467,6 +610,8 @@ interrupts = ; clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; clock-names = "tsadc", "apb_pclk"; + assigned-clocks = <&cru SCLK_TSADC>; + assigned-clock-rates = <10000>; resets = <&cru SRST_TSADC>; reset-names = "tsadc-apb"; pinctrl-names = "init", "default", "sleep"; @@ -481,8 +626,9 @@ gmac: ethernet@ff290000 { compatible = "rockchip,rk3288-gmac"; reg = <0xff290000 0x10000>; - interrupts = ; - interrupt-names = "macirq"; + interrupts = , + ; + interrupt-names = "macirq", "eth_wake_irq"; rockchip,grf = <&grf>; clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>, @@ -494,7 +640,6 @@ "aclk_mac", "pclk_mac"; resets = <&cru SRST_MAC>; reset-names = "stmmaceth"; - max-speed = <100>; status = "disabled"; }; @@ -550,17 +695,24 @@ status = "disabled"; }; - i2c0: i2c@ff650000 { - compatible = "rockchip,rk3288-i2c"; - reg = <0xff650000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_xfer>; - status = "disabled"; + dmc: dmc@ff610000 { + compatible = "rockchip,rk3288-dmc", "syscon"; + rockchip,cru = <&cru>; + rockchip,grf = <&grf>; + rockchip,pmu = <&pmu>; + rockchip,sgrf = <&sgrf>; + rockchip,noc = <&noc>; + reg = <0xff610000 0x3fc + 0xff620000 0x294 + 0xff630000 0x3fc + 0xff640000 0x294>; + rockchip,sram = <&ddr_sram>; + clocks = <&cru PCLK_DDRUPCTL0>, <&cru PCLK_PUBL0>, + <&cru PCLK_DDRUPCTL1>, <&cru PCLK_PUBL1>, + <&cru ARMCLK>, <&cru ACLK_DMAC1>; + clock-names = "pclk_ddrupctl0", "pclk_publ0", + "pclk_ddrupctl1", "pclk_publ1", + "arm_clk", "aclk_dmac1"; }; i2c2: i2c@ff660000 { @@ -630,6 +782,10 @@ compatible = "rockchip,rk3066-smp-sram"; reg = <0x00 0x10>; }; + ddr_sram: ddr-sram@1000 { + compatible = "rockchip,rk3288-ddr-sram"; + reg = <0x1000 0x4000>; + }; }; sram@ff720000 { @@ -740,7 +896,7 @@ * *_HDMI HDMI * *_MIPI_* MIPI */ - pd_vio { + pd_vio@RK3288_PD_VIO { reg = ; clocks = <&cru ACLK_IEP>, <&cru ACLK_ISP>, @@ -782,7 +938,7 @@ * Note: The following 3 are HEVC(H.265) clocks, * and on the ACLK_HEVC_NIU (NOC). */ - pd_hevc { + pd_hevc@RK3288_PD_HEVC { reg = ; clocks = <&cru ACLK_HEVC>, <&cru SCLK_HEVC_CABAC>, @@ -796,7 +952,7 @@ * (video endecoder & decoder) clocks that on the * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC). */ - pd_video { + pd_video@RK3288_PD_VIDEO { reg = ; clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; @@ -807,7 +963,7 @@ * Note: ACLK_GPU is the GPU clock, * and on the ACLK_GPU_NIU (NOC). */ - pd_gpu { + pd_gpu@RK3288_PD_GPU { reg = ; clocks = <&cru ACLK_GPU>; pm_qos = <&qos_gpu_r>, @@ -821,7 +977,7 @@ mode-normal = ; mode-recovery = ; mode-bootloader = ; - mode-loader = ; + mode-loader = ; mode-ums = ; }; }; @@ -853,8 +1009,56 @@ }; grf: syscon@ff770000 { - compatible = "rockchip,rk3288-grf", "syscon"; + compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd"; reg = <0xff770000 0x1000>; + + edp_phy: edp-phy { + compatible = "rockchip,rk3288-dp-phy"; + clocks = <&cru SCLK_EDP_24M>; + clock-names = "24m"; + #phy-cells = <0>; + status = "disabled"; + }; + + io_domains: io-domains { + compatible = "rockchip,rk3288-io-voltage-domain"; + status = "disabled"; + }; + + usbphy: usbphy { + compatible = "rockchip,rk3288-usb-phy"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + usbphy0: usb-phy@320 { + #phy-cells = <0>; + reg = <0x320>; + clocks = <&cru SCLK_OTGPHY0>; + clock-names = "phyclk"; + #clock-cells = <0>; + resets = <&cru SRST_USBOTG_PHY>; + reset-names = "phy-reset"; + }; + + usbphy1: usb-phy@334 { + #phy-cells = <0>; + reg = <0x334>; + clocks = <&cru SCLK_OTGPHY1>; + clock-names = "phyclk"; + #clock-cells = <0>; + }; + + usbphy2: usb-phy@348 { + #phy-cells = <0>; + reg = <0x348>; + clocks = <&cru SCLK_OTGPHY2>; + clock-names = "phyclk"; + #clock-cells = <0>; + resets = <&cru SRST_USBHOST1_PHY>; + reset-names = "phy-reset"; + }; + }; }; wdt: watchdog@ff800000 { @@ -892,6 +1096,42 @@ clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>; pinctrl-names = "default"; pinctrl-0 = <&i2s0_bus>; + rockchip,playback-channels = <8>; + rockchip,capture-channels = <2>; + status = "disabled"; + }; + + cif_isp0: cif_isp@ff910000 { + compatible = "rockchip,rk3288-cif-isp"; + rockchip,grf = <&grf>; + reg = <0xff910000 0x10000>, <0xff968000 0x4000>; + reg-names = "register", "csihost-register"; + clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>, + <&cru SCLK_ISP>, <&cru SCLK_ISP_JPE>, + <&cru PCLK_MIPI_CSI>, <&cru PCLK_ISP_IN>, + <&cru SCLK_MIPIDSI_24M>; + clock-names = "aclk_isp", "hclk_isp", + "sclk_isp", "sclk_isp_jpe", + "pclk_mipi_csi", "pclk_isp_in", + "sclk_mipidsi_24m"; + resets = <&cru SRST_ISP>; + reset-names = "rst_isp"; + interrupts = ; + interrupt-names = "cif_isp10_irq"; + status = "disabled"; + }; + + rga: rga@ff920000 { + compatible = "rockchip,rk3288-rga"; + reg = <0xff920000 0x180>; + interrupts = ; + interrupt-names = "rga"; + clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>; + clock-names = "aclk", "hclk", "sclk"; + power-domains = <&power RK3288_PD_VIO>; + resets = <&cru SRST_RGA_CORE>, <&cru SRST_RGA_AXI>, <&cru SRST_RGA_AHB>; + reset-names = "core", "axi", "ahb"; + dma-coherent; status = "disabled"; }; @@ -938,6 +1178,8 @@ reg = <0xff930300 0x100>; interrupts = ; interrupt-names = "vopb_mmu"; + clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; + clock-names = "aclk", "hclk"; power-domains = <&power RK3288_PD_VIO>; #iommu-cells = <0>; status = "disabled"; @@ -987,6 +1229,8 @@ reg = <0xff940300 0x100>; interrupts = ; interrupt-names = "vopl_mmu"; + clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; + clock-names = "aclk", "hclk"; power-domains = <&power RK3288_PD_VIO>; #iommu-cells = <0>; status = "disabled"; @@ -998,16 +1242,13 @@ interrupts = ; clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>; clock-names = "ref", "pclk"; + power-domains = <&power RK3288_PD_VIO>; rockchip,grf = <&grf>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; ports { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - mipi_in: port { #address-cells = <1>; #size-cells = <0>; @@ -1029,6 +1270,7 @@ interrupts = ; clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>; clock-names = "dp", "pclk"; + power-domains = <&power RK3288_PD_VIO>; phys = <&edp_phy>; phy-names = "dp"; resets = <&cru SRST_EDP>; @@ -1096,6 +1338,8 @@ interrupts = ; clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>; clock-names = "iahb", "isfr"; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_ddc>; power-domains = <&power RK3288_PD_VIO>; status = "disabled"; @@ -1115,32 +1359,6 @@ }; }; - gpu: gpu@ffa30000 { - compatible = "arm,malit764", - "arm,malit76x", - "arm,malit7xx", - "arm,mali-midgard"; - reg = <0xffa30000 0x10000>; - interrupts = , - , - ; - interrupt-names = "JOB", "MMU", "GPU"; - clocks = <&cru ACLK_GPU>; - clock-names = "clk_mali"; - operating-points = < - /* KHz uV */ - 600000 1250000 - /* 500000 1200000 - See crosbug.com/p/33857 */ - 400000 1100000 - 300000 1000000 - 200000 950000 - 100000 950000 - >; - #cooling-cells = <2>; /* min followed by max */ - power-domains = <&power RK3288_PD_GPU>; - status = "disabled"; - }; - vpu: video-codec@ff9a0000 { compatible = "rockchip,rk3288-vpu"; reg = <0xff9a0000 0x800>; @@ -1172,6 +1390,8 @@ iommu_enabled = <1>; dev_mode = <0>; status = "disabled"; + /* 0 means ion, 1 means drm */ + allocator = <1>; }; vpu_mmu: iommu@ff9a0800 { @@ -1179,6 +1399,8 @@ reg = <0xff9a0800 0x100>; interrupts = ; interrupt-names = "vpu_mmu"; + clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; + clock-names = "aclk", "hclk"; power-domains = <&power RK3288_PD_VIDEO>; #iommu-cells = <0>; }; @@ -1193,6 +1415,16 @@ <&cru SCLK_HEVC_CABAC>; clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core", "clk_cabac"; + /* + * The 4K hevc would also work well with 500/125/300/300, + * no more err irq and reset request. + */ + assigned-clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>, + <&cru SCLK_HEVC_CORE>, + <&cru SCLK_HEVC_CABAC>; + assigned-clock-rates = <400000000>, <100000000>, + <300000000>, <300000000>; + resets = <&cru SRST_HEVC>; reset-names = "video"; power-domains = <&power RK3288_PD_HEVC>; @@ -1201,6 +1433,8 @@ iommus = <&hevc_mmu>; iommu_enabled = <1>; status = "disabled"; + /* 0 means ion, 1 means drm */ + allocator = <1>; }; hevc_mmu: iommu@ff9c0440 { @@ -1208,21 +1442,74 @@ reg = <0xff9c0440 0x40>, <0xff9c0480 0x40>; interrupts = ; interrupt-names = "hevc_mmu"; + clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>, + <&cru SCLK_HEVC_CORE>, + <&cru SCLK_HEVC_CABAC>; + clock-names = "aclk", "hclk", "clk_core", + "clk_cabac"; power-domains = <&power RK3288_PD_HEVC>; #iommu-cells = <0>; }; - gic: interrupt-controller@ffc01000 { - compatible = "arm,gic-400"; - interrupt-controller; - #interrupt-cells = <3>; - #address-cells = <0>; + gpu: gpu@ffa30000 { + compatible = "arm,malit764", + "arm,malit76x", + "arm,malit7xx", + "arm,mali-midgard"; + reg = <0xffa30000 0x10000>; + interrupts = , + , + ; + interrupt-names = "JOB", "MMU", "GPU"; + clocks = <&cru ACLK_GPU>; + clock-names = "clk_mali"; + operating-points-v2 = <&gpu_opp_table>; + #cooling-cells = <2>; /* min followed by max */ + power-domains = <&power RK3288_PD_GPU>; + status = "disabled"; - reg = <0xffc01000 0x1000>, - <0xffc02000 0x1000>, - <0xffc04000 0x2000>, - <0xffc06000 0x2000>; - interrupts = ; + upthreshold = <75>; + downdifferential = <10>; + + gpu_power_model: power_model { + compatible = "arm,mali-simple-power-model"; + voltage = <950>; + frequency = <500>; + static-power = <300>; + dynamic-power = <396>; + ts = <32000 4700 (-80) 2>; + thermal-zone = "gpu_thermal"; + }; + }; + + gpu_opp_table: opp-table1 { + compatible = "operating-points-v2"; + + opp@100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <950000>; + }; + opp@200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <950000>; + }; + opp@300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <1000000>; + }; + opp@400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <1100000>; + }; + opp@600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1250000>; + }; + }; + + noc: syscon@ffac0000 { + compatible = "rockchip,rk3288-noc", "syscon"; + reg = <0xffac0000 0x2000>; }; efuse: efuse@ffb40000 { @@ -1238,33 +1525,17 @@ }; }; - usbphy: phy { - compatible = "rockchip,rk3288-usb-phy"; - rockchip,grf = <&grf>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - usbphy0: usb-phy0 { - #phy-cells = <0>; - reg = <0x320>; - clocks = <&cru SCLK_OTGPHY0>; - clock-names = "phyclk"; - }; - - usbphy1: usb-phy1 { - #phy-cells = <0>; - reg = <0x334>; - clocks = <&cru SCLK_OTGPHY1>; - clock-names = "phyclk"; - }; + gic: interrupt-controller@ffc01000 { + compatible = "arm,gic-400"; + interrupt-controller; + #interrupt-cells = <3>; + #address-cells = <0>; - usbphy2: usb-phy2 { - #phy-cells = <0>; - reg = <0x348>; - clocks = <&cru SCLK_OTGPHY2>; - clock-names = "phyclk"; - }; + reg = <0xffc01000 0x1000>, + <0xffc02000 0x1000>, + <0xffc04000 0x2000>, + <0xffc06000 0x2000>; + interrupts = ; }; pinctrl: pinctrl { @@ -1835,5 +2106,21 @@ rockchip,pins = ; }; }; + + cif { + cif_dvp_d2d9: cif-dvp-d2d9 { + rockchip,pins = <2 0 RK_FUNC_1 &pcfg_pull_none>, + <2 1 RK_FUNC_1 &pcfg_pull_none>, + <2 2 RK_FUNC_1 &pcfg_pull_none>, + <2 3 RK_FUNC_1 &pcfg_pull_none>, + <2 4 RK_FUNC_1 &pcfg_pull_none>, + <2 5 RK_FUNC_1 &pcfg_pull_none>, + <2 6 RK_FUNC_1 &pcfg_pull_none>, + <2 7 RK_FUNC_1 &pcfg_pull_none>, + <2 8 RK_FUNC_1 &pcfg_pull_none>, + <2 9 RK_FUNC_1 &pcfg_pull_none>, + <2 11 RK_FUNC_1 &pcfg_pull_none>; + }; + }; }; };