drm/rockchip: gem: add get phys ioctl

[firefly-linux-kernel-4.4.55.git] / include / uapi / drm / rockchip_drm.h

diff --git a/include/uapi/drm/rockchip_drm.h b/include/uapi/drm/rockchip_drm.h
index b8f367d9114d2e6bb23793b428281244d1ffed16..58e557548b3a6c4e631d754bdea96ec83f79f998 100644 (file)
--- a/include/uapi/drm/rockchip_drm.h
+++ b/include/uapi/drm/rockchip_drm.h
@@ -17,6 +17,18 @@
 
 #include <drm/drm.h>
 
+/* memory type definitions. */
+enum drm_rockchip_gem_mem_type {
+       /* Physically Continuous memory. */
+       ROCKCHIP_BO_CONTIG      = 1 << 0,
+       /* cachable mapping. */
+       ROCKCHIP_BO_CACHABLE    = 1 << 1,
+       /* write-combine mapping. */
+       ROCKCHIP_BO_WC          = 1 << 2,
+       ROCKCHIP_BO_MASK        = ROCKCHIP_BO_CONTIG | ROCKCHIP_BO_CACHABLE |
+                               ROCKCHIP_BO_WC
+};
+
 /**
  * User-desired buffer creation information structure.
  *
@@ -31,6 +43,11 @@ struct drm_rockchip_gem_create {
        uint32_t handle;
 };
 
+struct drm_rockchip_gem_phys {
+       uint32_t handle;
+       uint32_t phy_addr;
+};
+
 /**
  * A structure for getting buffer offset.
  *
@@ -71,10 +88,60 @@ struct drm_rockchip_gem_cpu_release {
        uint32_t handle;
 };
 
+struct drm_rockchip_rga_get_ver {
+       __u32   major;
+       __u32   minor;
+};
+
+struct drm_rockchip_rga_cmd {
+       __u32   offset;
+       __u32   data;
+};
+
+enum drm_rockchip_rga_buf_type {
+       RGA_BUF_TYPE_USERPTR = 1 << 31,
+       RGA_BUF_TYPE_GEMFD   = 1 << 30,
+       RGA_BUF_TYPE_FLUSH   = 1 << 29,
+};
+
+struct drm_rockchip_rga_set_cmdlist {
+       __u64           cmd;
+       __u64           cmd_buf;
+       __u32           cmd_nr;
+       __u32           cmd_buf_nr;
+       __u64           user_data;
+};
+
+struct drm_rockchip_rga_exec {
+       __u64           async;
+};
+
+enum rockchip_plane_feture {
+       ROCKCHIP_DRM_PLANE_FEATURE_SCALE,
+       ROCKCHIP_DRM_PLANE_FEATURE_ALPHA,
+       ROCKCHIP_DRM_PLANE_FEATURE_MAX,
+};
+
+enum rockchip_crtc_feture {
+       ROCKCHIP_DRM_CRTC_FEATURE_AFBDC,
+};
+
+enum rockchip_cabc_mode {
+       ROCKCHIP_DRM_CABC_MODE_DISABLE,
+       ROCKCHIP_DRM_CABC_MODE_NORMAL,
+       ROCKCHIP_DRM_CABC_MODE_LOWPOWER,
+       ROCKCHIP_DRM_CABC_MODE_USERSPACE,
+};
+
 #define DRM_ROCKCHIP_GEM_CREATE                0x00
 #define DRM_ROCKCHIP_GEM_MAP_OFFSET    0x01
 #define DRM_ROCKCHIP_GEM_CPU_ACQUIRE   0x02
 #define DRM_ROCKCHIP_GEM_CPU_RELEASE   0x03
+#define DRM_ROCKCHIP_GEM_GET_PHYS      0x04
+
+#define DRM_ROCKCHIP_RGA_GET_VER       0x20
+#define DRM_ROCKCHIP_RGA_SET_CMDLIST   0x21
+#define DRM_ROCKCHIP_RGA_EXEC          0x22
 
 #define DRM_IOCTL_ROCKCHIP_GEM_CREATE  DRM_IOWR(DRM_COMMAND_BASE + \
                DRM_ROCKCHIP_GEM_CREATE, struct drm_rockchip_gem_create)
@@ -88,4 +155,16 @@ struct drm_rockchip_gem_cpu_release {
 #define DRM_IOCTL_ROCKCHIP_GEM_CPU_RELEASE     DRM_IOWR(DRM_COMMAND_BASE + \
                DRM_ROCKCHIP_GEM_CPU_RELEASE, struct drm_rockchip_gem_cpu_release)
 
+#define DRM_IOCTL_ROCKCHIP_GEM_GET_PHYS                DRM_IOWR(DRM_COMMAND_BASE + \
+               DRM_ROCKCHIP_GEM_GET_PHYS, struct drm_rockchip_gem_phys)
+
+#define DRM_IOCTL_ROCKCHIP_RGA_GET_VER         DRM_IOWR(DRM_COMMAND_BASE + \
+               DRM_ROCKCHIP_RGA_GET_VER, struct drm_rockchip_rga_get_ver)
+
+#define DRM_IOCTL_ROCKCHIP_RGA_SET_CMDLIST     DRM_IOWR(DRM_COMMAND_BASE + \
+               DRM_ROCKCHIP_RGA_SET_CMDLIST, struct drm_rockchip_rga_set_cmdlist)
+
+#define DRM_IOCTL_ROCKCHIP_RGA_EXEC            DRM_IOWR(DRM_COMMAND_BASE + \
+               DRM_ROCKCHIP_RGA_EXEC, struct drm_rockchip_rga_exec)
+
 #endif /* _UAPI_ROCKCHIP_DRM_H */