#define __MACH_ROCKCHIP_CRU_H
#include <dt-bindings/clock/rockchip,rk3188.h>
+#include <dt-bindings/clock/rockchip,rk3288.h>
#include <linux/rockchip/iomap.h>
#define RK3288_CRU_CLKGATES_CON(i) (RK3288_CRU_CLKGATE_CON + ((i) * 4))
/******************PLL MODE BITS*******************/
-// apll dpll,cpll,gpll,npll 0~4
+/*************apll dpll,cpll,gpll,npll 0~4************/
#define RK3288_PLLS_MODE_OFFSET(id) ((id)<=3 ? (id*4) : 14)
#define RK3288_PLL_MODE_MSK(id) (0x3 << RK3288_PLLS_MODE_OFFSET(id))
#define RK3288_PLL_MODE_SLOW(id) ((0x0<<RK3288_PLLS_MODE_OFFSET(id))|(0x3<<(16+RK3288_PLLS_MODE_OFFSET(id))))
enum rk3288_cru_clk_gate {
/* SCU CLK GATE 0 CON */
- //gate0
RK3288_CLKGATE_UART0_SRC = (RK3288_CRU_CONS_GATEID(1)+8),
RK3288_CLKGATE_UART4_SRC = (RK3288_CRU_CONS_GATEID(2)+12),
#define RK3288_CRU_SOFTRSTS_CON_CNT (12)
#define RK3288_CRU_SOFTRSTS_CON(i) (RK3288_CRU_SOFTRST_CON + ((i) * 4))
-enum rk3288_cru_soft_reset {
- RK3288_SOFT_RST_CORE0,
- RK3288_SOFT_RST_CORE1,
- RK3288_SOFT_RST_CORE2,
- RK3288_SOFT_RST_CORE3,
- RK3288_SOFT_RST_CORE0_PO,
- RK3288_SOFT_RST_CORE1_PO,
- RK3288_SOFT_RST_CORE2_PO,
- RK3288_SOFT_RST_CORE3_PO,
- RK3288_SOFT_RST_PD_CORE_STR_SYS_A,
- RK3288_SOFT_RST_PD_BUS_STR_SYS_A,
- RK3288_SOFT_RST_L2C,
- RK3288_SOFT_RST_TOPDBG,
- RK3288_SOFT_RST_CORE0_DBG,
- RK3288_SOFT_RST_CORE1_DBG,
- RK3288_SOFT_RST_CORE2_DBG,
- RK3288_SOFT_RST_CORE3_DBG,
-
- RK3288_SOFT_RST_PD_BUS_AHB_ARBITOR,
- RK3288_SOFT_RST_EFUSE_256BIT_P,
- RK3288_SOFT_RST_DMA1,
- RK3288_SOFT_RST_INTMEM,
- RK3288_SOFT_RST_ROM,
- RK3288_SOFT_RST_SPDIF_8CH,
- RK3288_SOFT_RST_TIMER_P,
- RK3288_SOFT_RST_I2S,
- RK3288_SOFT_RST_SPDIF,
- RK3288_SOFT_RST_TIMER0,
- RK3288_SOFT_RST_TIMER1,
- RK3288_SOFT_RST_TIMER2,
- RK3288_SOFT_RST_TIMER3,
- RK3288_SOFT_RST_TIMER4,
- RK3288_SOFT_RST_TIMER5,
- RK3288_SOFT_RST_EFUSE_P,
-
- RK3288_SOFT_RST_GPIO0,
- RK3288_SOFT_RST_GPIO1,
- RK3288_SOFT_RST_GPIO2,
- RK3288_SOFT_RST_GPIO3,
- RK3288_SOFT_RST_GPIO4,
- RK3288_SOFT_RST_GPIO5,
- RK3288_SOFT_RST_GPIO6,
- RK3288_SOFT_RST_GPIO7,
- RK3288_SOFT_RST_GPIO8,
- RK3288_SOFT_RST_2RES9,
- RK3288_SOFT_RST_I2C0,
- RK3288_SOFT_RST_I2C1,
- RK3288_SOFT_RST_I2C2,
- RK3288_SOFT_RST_I2C3,
- RK3288_SOFT_RST_I2C4,
- RK3288_SOFT_RST_I2C5,
-
- RK3288_SOFT_RST_DW_PWM,
- RK3288_SOFT_RST_MMC_PERI,
- RK3288_SOFT_RST_PERIPH_MMU,
- RK3288_SOFT_RST_DAP,
- RK3288_SOFT_RST_DAP_SYS,
- RK3288_SOFT_RST_TPIU_AT,
- RK3288_SOFT_RST_PMU_P,
- RK3288_SOFT_RST_GRF,
- RK3288_SOFT_RST_PMU,
- RK3288_SOFT_RST_PERIPHSYS_A,
- RK3288_SOFT_RST_PERIPHSYS_H,
- RK3288_SOFT_RST_PERIPHSYS_P,
- RK3288_SOFT_RST_PERIPH_NIU,
- RK3288_SOFT_RST_PD_PERI_AHB_ARBITOR,
- RK3288_SOFT_RST_EMEM_PERI,
- RK3288_SOFT_RST_USB_PERI,
-
- RK3288_SOFT_RST_DMA2,
- RK3288_SOFT_RST_4RES1,
- RK3288_SOFT_RST_MAC,
- RK3288_SOFT_RST_GPS,
- RK3288_SOFT_RST_4RES4,
- RK3288_SOFT_RST_RK_PWM,
- RK3288_SOFT_RST_4RES6,
- RK3288_SOFT_RST_CCP,
- RK3288_SOFT_RST_USB_HOST0,
- RK3288_SOFT_RST_HSIC,
- RK3288_SOFT_RST_HSIC_AUX,
- RK3288_SOFT_RST_HSICPHY,
- RK3288_SOFT_RST_HSADC,
- RK3288_SOFT_RST_NANDC0,
- RK3288_SOFT_RST_NANDC1,
- RK3288_SOFT_RST_4RES15,
-
- RK3288_SOFT_RST_TZPC,
- RK3288_SOFT_RST_5RES1,
- RK3288_SOFT_RST_5RES2,
- RK3288_SOFT_RST_SPI0,
- RK3288_SOFT_RST_SPI1,
- RK3288_SOFT_RST_SPI2,
- RK3288_SOFT_RST_5RES6,
- RK3288_SOFT_RST_SARADC,
- RK3288_SOFT_RST_PD_ALIVE_NIU_P,
- RK3288_SOFT_RST_PD_PMU_INTMEM_P,
- RK3288_SOFT_RST_PD_PMU_NIU_P,
- RK3288_SOFT_RST_SECURITY_GRF_P,
- RK3288_SOFT_RST_5RES12,
- RK3288_SOFT_RST_5RES13,
- RK3288_SOFT_RST_5RES14,
- RK3288_SOFT_RST_5RES15,
-
- RK3288_SOFT_RST_VIO_ARBI_H,
- RK3288_SOFT_RST_RGA_NIU_A,
- RK3288_SOFT_RST_VIO0_NIU_A,
- RK3288_SOFT_RST_VIO_NIU_H,
- RK3288_SOFT_RST_LCDC0_A,
- RK3288_SOFT_RST_LCDC0_H,
- RK3288_SOFT_RST_LCDC0_D,
- RK3288_SOFT_RST_VIO1_NIU_A,
- RK3288_SOFT_RST_VIP,
- RK3288_SOFT_RST_RGA_CORE,
- RK3288_SOFT_RST_IEP_A,
- RK3288_SOFT_RST_IEP_H,
- RK3288_SOFT_RST_RGA_A,
- RK3288_SOFT_RST_RGA_H,
- RK3288_SOFT_RST_ISP,
- RK3288_SOFT_RST_EDP,
-
- RK3288_SOFT_RST_VCODEC_A,
- RK3288_SOFT_RST_VCODEC_H,
- RK3288_SOFT_RST_VIO_H2P_H,
- RK3288_SOFT_RST_MIPIDSI0_P,
- RK3288_SOFT_RST_MIPIDSI1_P,
- RK3288_SOFT_RST_MIPICSI_P,
- RK3288_SOFT_RST_LVDS_PHY_P,
- RK3288_SOFT_RST_LVDS_CON,
- RK3288_SOFT_RST_GPU,
- RK3288_SOFT_RST_HDMI,
- RK3288_SOFT_RST_7RES10,
- RK3288_SOFT_RST_7RES11,
- RK3288_SOFT_RST_CORE_PVTM,
- RK3288_SOFT_RST_GPU_PVTM,
- RK3288_SOFT_RST_7RES14,
- RK3288_SOFT_RST_7RES15,
-
- RK3288_SOFT_RST_MMC0,
- RK3288_SOFT_RST_SDIO0,
- RK3288_SOFT_RST_SDIO1,
- RK3288_SOFT_RST_EMMC,
- RK3288_SOFT_RST_USBOTG_H,
- RK3288_SOFT_RST_USBOTGPHY,
- RK3288_SOFT_RST_USBOTGC,
- RK3288_SOFT_RST_USBHOST0_H,
- RK3288_SOFT_RST_USBHOST0PHY,
- RK3288_SOFT_RST_USBHOST0C,
- RK3288_SOFT_RST_USBHOST1_H,
- RK3288_SOFT_RST_USBHOST1PHY,
- RK3288_SOFT_RST_USBHOST1C,
- RK3288_SOFT_RST_USB_ADP,
- RK3288_SOFT_RST_ACC_EFUSE,
- RK3288_SOFT_RST_8RES15,
-
- RK3288_SOFT_RST_CORESIGHT,
- RK3288_SOFT_RST_PD_CORE_AHB_NOC,
- RK3288_SOFT_RST_PD_CORE_APB_NOC,
- RK3288_SOFT_RST_PD_CORE_MP_AXI,
- RK3288_SOFT_RST_GIC,
- RK3288_SOFT_RST_LCDCPWM0,
- RK3288_SOFT_RST_LCDCPWM1,
- RK3288_SOFT_RST_VIO0_H2P_BRG,
- RK3288_SOFT_RST_VIO1_H2P_BRG,
- RK3288_SOFT_RST_RGA_H2P_BRG,
- RK3288_SOFT_RST_HEVC,
- RK3288_SOFT_RST_9RES11,
- RK3288_SOFT_RST_9RES12,
- RK3288_SOFT_RST_9RES13,
- RK3288_SOFT_RST_9RES14,
- RK3288_SOFT_RST_TSADC_P,
-
- RK3288_SOFT_RST_DDRPHY0,
- RK3288_SOFT_RST_DDRPHY0_P,
- RK3288_SOFT_RST_DDRCTRL0,
- RK3288_SOFT_RST_DDRCTRL0_P,
- RK3288_SOFT_RST_DDRPHY0_CTL,
- RK3288_SOFT_RST_DDRPHY1,
- RK3288_SOFT_RST_DDRPHY1_P,
- RK3288_SOFT_RST_DDRCTRL1,
- RK3288_SOFT_RST_DDRCTRL1_P,
- RK3288_SOFT_RST_DDRPHY1_CTL,
- RK3288_SOFT_RST_DDRMSCH0,
- RK3288_SOFT_RST_DDRMSCH1,
- RK3288_SOFT_RST_10RES12,
- RK3288_SOFT_RST_10RES13,
- RK3288_SOFT_RST_CRYPTO,
- RK3288_SOFT_RST_C2C_HOST,
-
- RK3288_SOFT_RST_LCDC1_A,
- RK3288_SOFT_RST_LCDC1_H,
- RK3288_SOFT_RST_LCDC1_D,
- RK3288_SOFT_RST_UART0,
- RK3288_SOFT_RST_UART1,
- RK3288_SOFT_RST_UART2,
- RK3288_SOFT_RST_UART3,
- RK3288_SOFT_RST_UART4,
- RK3288_SOFT_RST_11RES8,
- RK3288_SOFT_RST_11RES9,
- RK3288_SOFT_RST_SIMC,
- RK3288_SOFT_RST_PS2C,
- RK3288_SOFT_RST_TSP,
- RK3288_SOFT_RST_TSP_CLKIN0,
- RK3288_SOFT_RST_TSP_CLKIN1,
- RK3288_SOFT_RST_TSP_27M,
-};
-
-static inline void rk3288_cru_set_soft_reset(enum rk3288_cru_soft_reset idx, bool on)
+static inline void rk3288_cru_set_soft_reset(u32 idx, bool on)
{
void __iomem *reg = RK_CRU_VIRT + RK3288_CRU_SOFTRSTS_CON(idx >> 4);
u32 val = on ? 0x10001U << (idx & 0xf) : 0x10000U << (idx & 0xf);
writel_relaxed(val, reg);
- dsb();
+ dsb(sy);
}
+#define RK3036_CRU_MODE_CON 0x0040
+
+/******************PLL MODE BITS*******************/
+/****************apll dpll,gpll 0~2******************/
+#define RK3036_PLLS_MODE_OFFSET(id) ((id) < 2 ? (id*4) : 12)
+
+#define RK3036_PLL_MODE_SLOW(id) ((0x0 << RK3036_PLLS_MODE_OFFSET(id)) \
+ | (((id) < 2 ? 0x1 : 0x3) << (16 + RK3036_PLLS_MODE_OFFSET(id))))
+
+#define RK3036_PLL_MODE_MSK(id) (0x1 << RK3036_PLLS_MODE_OFFSET(id))
+
+#define RK3036_APLL_MODE_SLOW ((0x0<<0x00)|(0x1<<(16+0x00)))
+#define RK3036_DPLL_MODE_SLOW ((0x0<<0x04)|(0x1<<(16+0x04)))
+#define RK3036_GPLL_MODE_SLOW ((0x0<<0x12)|(0x3<<(16+0x12)))
+
+#define RK3036_APLL_MODE_NORM ((0x1<<0x00)|(0x1<<(16+0x00)))
+#define RK3036_DPLL_MODE_NORM ((0x1<<0x04)|(0x1<<(16+0x04)))
+#define RK3036_GPLL_MODE_NORM ((0x1<<0x12)|(0x3<<(16+0x12)))
+
+#define RK3036_GPLL_MODE_DEEP ((0x10<<0x12)|(0x3<<(16+0x12)))
+
+#define RK3036_PLL_CONS(id, i) (((id) < 2 ? id : (id + 1)) * 0x10 + ((i) * 4))
+
+#define RK3036_CRU_GLB_SRST_FST_VALUE 0x00100
+#define RK3036_CRU_GLB_SRST_SND_VALUE 0x00104
+#define RK3036_CRU_SOFTRST0_CON 0x00110
+#define RK3036_CRU_SOFTRST1_CON 0x00114
+#define RK3036_CRU_SOFTRST2_CON 0x00118
+#define RK3036_CRU_SOFTRST3_CON 0x0011c
+#define RK3036_CRU_SOFTRST4_CON 0x00120
+#define RK3036_CRU_SOFTRST5_CON 0x00124
+#define RK3036_CRU_SOFTRST6_CON 0x00128
+#define RK3036_CRU_SOFTRST7_CON 0x0012c
+#define RK3036_CRU_SOFTRST8_CON 0x00130
+#define RK3036_CRU_MISC_CON 0x00134
+#define RK3036_CRU_GLB_CNT_TH 0x00140
+#define RK3036_CRU_SDMMC_CON0 0x00144
+#define RK3036_CRU_SDMMC_CON1 0x00148
+#define RK3036_CRU_SDIO_CON0 0x0014c
+#define RK3036_CRU_SDIO_CON1 0x00150
+#define RK3036_CRU_EMMC_CON0 0x00154
+#define RK3036_CRU_EMMC_CON1 0x00158
+#define RK3036_CRU_RST_ST 0x00160
+#define RK3036_CRU_PLL_MASK_CON 0x001f0
+
+#define RK3036_CRU_CLKSEL_CON 0x44
+#define RK3036_CRU_CLKGATE_CON 0xd0
+
+#define RK3036_CRU_CLKSELS_CON_CNT (35)
+#define RK3036_CRU_CLKSELS_CON(i) (RK3036_CRU_CLKSEL_CON + ((i) * 4))
+
+#define RK3036_CRU_CLKGATES_CON_CNT (11)
+#define RK3036_CRU_CLKGATES_CON(i) (RK3036_CRU_CLKGATE_CON + ((i) * 4))
+
+#define RK3036_CRU_SOFTRSTS_CON_CNT (9)
+#define RK3036_CRU_SOFTRSTS_CON(i) (RK3036_CRU_SOFTRST_CON + ((i) * 4))
+
+/*******************CRU GATING*********************/
+#define RK3036_CRU_UART_GATE 0xd4
+#define RK3036_CLKGATE_UART0_SRC 8
+#define RK3036_CLKGATE_UART0_PCLK 9
+
+#define RK312X_PLL_CONS(id, i) ((id) * 0x10 + ((i) * 4))
+
+#define RK312X_CRU_GLB_SRST_FST_VALUE 0x00100
+#define RK312X_CRU_GLB_SRST_SND_VALUE 0x00104
+#define RK312X_CRU_MISC_CON 0x00134
+#define RK312X_CRU_GLB_CNT_TH 0x00140
+#define RK312X_CRU_GLB_RST_ST 0x00150
+#define RK312X_CRU_SDMMC_CON0 0x01c0
+#define RK312X_CRU_SDMMC_CON1 0x01c4
+#define RK312X_CRU_SDIO_CON0 0x01c8
+#define RK312X_CRU_SDIO_CON1 0x01cc
+#define RK312X_CRU_EMMC_CON0 0x01d8
+#define RK312X_CRU_EMMC_CON1 0x01dc
+#define RK312X_CRU_PLL_PRG_EN 0x01f0
+#define RK312X_CRU_MODE_CON 0x40
+#define RK312X_CRU_RST_ST 0x00160
+#define RK312X_CRU_PLL_MASK_CON 0x001f0
+
+#define RK312X_CRU_CLKSEL_CON 0x44
+#define RK312X_CRU_CLKGATE_CON 0xd0
+
+#define RK312X_PLL_CONS(id, i) ((id) * 0x10 + ((i) * 4))
+
+/******************PLL MODE BITS*******************/
+#define RK312X_PLLS_MODE_OFFSET(id) ((id) <= 3 ? (id * 4) : 14)
+#define RK312X_PLL_MODE_MSK(id) (0x1 << RK312X_PLLS_MODE_OFFSET(id))
+#define RK312X_PLL_MODE_SLOW(id) ((0x0 << RK312X_PLLS_MODE_OFFSET(id))\
+| (0x1 << (16 + RK312X_PLLS_MODE_OFFSET(id))))
+#define RK312X_PLL_MODE_NORM(id) ((0x1 << RK312X_PLLS_MODE_OFFSET(id))\
+| (0x1 << (16 + RK312X_PLLS_MODE_OFFSET(id))))
+
+
+#define RK312X_CRU_SOFTRST_CON 0x110
+
+#define RK312X_CRU_CLKSELS_CON_CNT (35)
+#define RK312X_CRU_CLKSELS_CON(i) (RK3036_CRU_CLKSEL_CON + ((i) * 4))
+
+#define RK312X_CRU_CLKGATES_CON_CNT (11)
+#define RK312X_CRU_CLKGATES_CON(i) (RK3036_CRU_CLKGATE_CON + ((i) * 4))
+
+#define RK312X_CRU_SOFTRSTS_CON_CNT (9)
+#define RK312X_CRU_SOFTRSTS_CON(i) (RK312X_CRU_SOFTRST_CON + ((i) * 4))
+
+/*******************CRU GATING*********************/
+#define RK312X_CRU_CONS_GATEID(i) (16 * (i))
+#define RK312X_CRU_GATEID_CONS(ID) (RK312X_CRU_CLKGATE_CON\
+ + ((ID) / 16) * 4)
+
+enum rk312x_cru_clk_gate {
+ /* SCU CLK GATE 0 CON */
+ RK312X_CLKGATE_UART0_SRC = (RK312X_CRU_CONS_GATEID(1) + 8),
+ RK312X_CLKGATE_PCLK_UART0 = (RK312X_CRU_CONS_GATEID(8) + 0),
+ RK312X_CLKGATE_PCLK_UART1,
+ RK312X_CLKGATE_PCLK_UART2,
+};
+
+/*************************RK3368********************************/
+
+/*******************CRU OFFSET*********************/
+#define RK3368_CRU_CLKSEL_CON 0x100
+#define RK3368_CRU_CLKGATE_CON 0x200
+#define RK3368_CRU_CLKGATES_CON_CNT 25
+
+#define RK3368_PLL_CONS(id, i) ((id) * 0x10 + ((i) * 4))
+#define RK3368_CRU_CLKSELS_CON(i) (RK3368_CRU_CLKSEL_CON + ((i) * 4))
+#define RK3368_CRU_CLKGATES_CON(i) (RK3368_CRU_CLKGATE_CON + ((i) * 4))
+
+#define RK3368_CRU_SOFTRSTS_CON_CNT (15)
+#define RK3368_CRU_SOFTRST_CON 0x300
+#define RK3368_CRU_SOFTRSTS_CON(i) (RK3368_CRU_SOFTRST_CON + ((i) * 4))
+
#endif
projects / firefly-linux-kernel-4.4.55.git / blobdiff