+/*******************CRU GATING*********************/
+#define RK3036_CRU_UART_GATE 0xd4
+#define RK3036_CLKGATE_UART0_SRC 8
+#define RK3036_CLKGATE_UART0_PCLK 9
+
+#define RK312X_PLL_CONS(id, i) ((id) * 0x10 + ((i) * 4))
+
+#define RK312X_CRU_GLB_SRST_FST_VALUE 0x00100
+#define RK312X_CRU_GLB_SRST_SND_VALUE 0x00104
+#define RK312X_CRU_MISC_CON 0x00134
+#define RK312X_CRU_GLB_CNT_TH 0x00140
+#define RK312X_CRU_GLB_RST_ST 0x00150
+#define RK312X_CRU_SDMMC_CON0 0x01c0
+#define RK312X_CRU_SDMMC_CON1 0x01c4
+#define RK312X_CRU_SDIO_CON0 0x01c8
+#define RK312X_CRU_SDIO_CON1 0x01cc
+#define RK312X_CRU_EMMC_CON0 0x01d8
+#define RK312X_CRU_EMMC_CON1 0x01dc
+#define RK312X_CRU_PLL_PRG_EN 0x01f0
+#define RK312X_CRU_MODE_CON 0x40
+#define RK312X_CRU_RST_ST 0x00160
+#define RK312X_CRU_PLL_MASK_CON 0x001f0
+
+#define RK312X_CRU_CLKSEL_CON 0x44
+#define RK312X_CRU_CLKGATE_CON 0xd0
+
+#define RK312X_PLL_CONS(id, i) ((id) * 0x10 + ((i) * 4))
+
+/******************PLL MODE BITS*******************/
+#define RK312X_PLLS_MODE_OFFSET(id) ((id) <= 3 ? (id * 4) : 14)
+#define RK312X_PLL_MODE_MSK(id) (0x1 << RK312X_PLLS_MODE_OFFSET(id))
+#define RK312X_PLL_MODE_SLOW(id) ((0x0 << RK312X_PLLS_MODE_OFFSET(id))\
+| (0x1 << (16 + RK312X_PLLS_MODE_OFFSET(id))))
+#define RK312X_PLL_MODE_NORM(id) ((0x1 << RK312X_PLLS_MODE_OFFSET(id))\
+| (0x1 << (16 + RK312X_PLLS_MODE_OFFSET(id))))
+
+