#define RK3288_CRU_CLKGATES_CON(i) (RK3288_CRU_CLKGATE_CON + ((i) * 4))
/******************PLL MODE BITS*******************/
-// apll dpll,cpll,gpll,npll 0~4
+/*************apll dpll,cpll,gpll,npll 0~4************/
#define RK3288_PLLS_MODE_OFFSET(id) ((id)<=3 ? (id*4) : 14)
#define RK3288_PLL_MODE_MSK(id) (0x3 << RK3288_PLLS_MODE_OFFSET(id))
#define RK3288_PLL_MODE_SLOW(id) ((0x0<<RK3288_PLLS_MODE_OFFSET(id))|(0x3<<(16+RK3288_PLLS_MODE_OFFSET(id))))
enum rk3288_cru_clk_gate {
/* SCU CLK GATE 0 CON */
- //gate0
RK3288_CLKGATE_UART0_SRC = (RK3288_CRU_CONS_GATEID(1)+8),
RK3288_CLKGATE_UART4_SRC = (RK3288_CRU_CONS_GATEID(2)+12),
void __iomem *reg = RK_CRU_VIRT + RK3288_CRU_SOFTRSTS_CON(idx >> 4);
u32 val = on ? 0x10001U << (idx & 0xf) : 0x10000U << (idx & 0xf);
writel_relaxed(val, reg);
- dsb();
+ dsb(sy);
}
#define RK3036_CRU_MODE_CON 0x0040
+/******************PLL MODE BITS*******************/
+/****************apll dpll,gpll 0~2******************/
+#define RK3036_PLLS_MODE_OFFSET(id) ((id) < 2 ? (id*4) : 12)
+
+#define RK3036_PLL_MODE_SLOW(id) ((0x0 << RK3036_PLLS_MODE_OFFSET(id)) \
+ | (((id) < 2 ? 0x1 : 0x3) << (16 + RK3036_PLLS_MODE_OFFSET(id))))
+
+#define RK3036_PLL_MODE_MSK(id) (0x1 << RK3036_PLLS_MODE_OFFSET(id))
+
+#define RK3036_APLL_MODE_SLOW ((0x0<<0x00)|(0x1<<(16+0x00)))
+#define RK3036_DPLL_MODE_SLOW ((0x0<<0x04)|(0x1<<(16+0x04)))
+#define RK3036_GPLL_MODE_SLOW ((0x0<<0x12)|(0x3<<(16+0x12)))
+
+#define RK3036_APLL_MODE_NORM ((0x1<<0x00)|(0x1<<(16+0x00)))
+#define RK3036_DPLL_MODE_NORM ((0x1<<0x04)|(0x1<<(16+0x04)))
+#define RK3036_GPLL_MODE_NORM ((0x1<<0x12)|(0x3<<(16+0x12)))
+
+#define RK3036_GPLL_MODE_DEEP ((0x10<<0x12)|(0x3<<(16+0x12)))
+
+#define RK3036_PLL_CONS(id, i) (((id) < 2 ? id : (id + 1)) * 0x10 + ((i) * 4))
+
#define RK3036_CRU_GLB_SRST_FST_VALUE 0x00100
#define RK3036_CRU_GLB_SRST_SND_VALUE 0x00104
#define RK3036_CRU_SOFTRST0_CON 0x00110
#define RK3036_CRU_CLKSELS_CON_CNT (35)
#define RK3036_CRU_CLKSELS_CON(i) (RK3036_CRU_CLKSEL_CON + ((i) * 4))
-#define RK3036_CRU_CLKGATES_CON_CNT (10)
+#define RK3036_CRU_CLKGATES_CON_CNT (11)
#define RK3036_CRU_CLKGATES_CON(i) (RK3036_CRU_CLKGATE_CON + ((i) * 4))
#define RK3036_CRU_SOFTRSTS_CON_CNT (9)
#define RK3036_CRU_SOFTRSTS_CON(i) (RK3036_CRU_SOFTRST_CON + ((i) * 4))
+/*******************CRU GATING*********************/
+#define RK3036_CRU_UART_GATE 0xd4
+#define RK3036_CLKGATE_UART0_SRC 8
+#define RK3036_CLKGATE_UART0_PCLK 9
+
+#define RK312X_PLL_CONS(id, i) ((id) * 0x10 + ((i) * 4))
+
+#define RK312X_CRU_GLB_SRST_FST_VALUE 0x00100
+#define RK312X_CRU_GLB_SRST_SND_VALUE 0x00104
+#define RK312X_CRU_MISC_CON 0x00134
+#define RK312X_CRU_GLB_CNT_TH 0x00140
+#define RK312X_CRU_GLB_RST_ST 0x00150
+#define RK312X_CRU_SDMMC_CON0 0x01c0
+#define RK312X_CRU_SDMMC_CON1 0x01c4
+#define RK312X_CRU_SDIO_CON0 0x01c8
+#define RK312X_CRU_SDIO_CON1 0x01cc
+#define RK312X_CRU_EMMC_CON0 0x01d8
+#define RK312X_CRU_EMMC_CON1 0x01dc
+#define RK312X_CRU_PLL_PRG_EN 0x01f0
+#define RK312X_CRU_MODE_CON 0x40
+#define RK312X_CRU_RST_ST 0x00160
+#define RK312X_CRU_PLL_MASK_CON 0x001f0
+
+#define RK312X_CRU_CLKSEL_CON 0x44
+#define RK312X_CRU_CLKGATE_CON 0xd0
+
+#define RK312X_PLL_CONS(id, i) ((id) * 0x10 + ((i) * 4))
+
+/******************PLL MODE BITS*******************/
+#define RK312X_PLLS_MODE_OFFSET(id) ((id) <= 3 ? (id * 4) : 14)
+#define RK312X_PLL_MODE_MSK(id) (0x1 << RK312X_PLLS_MODE_OFFSET(id))
+#define RK312X_PLL_MODE_SLOW(id) ((0x0 << RK312X_PLLS_MODE_OFFSET(id))\
+| (0x1 << (16 + RK312X_PLLS_MODE_OFFSET(id))))
+#define RK312X_PLL_MODE_NORM(id) ((0x1 << RK312X_PLLS_MODE_OFFSET(id))\
+| (0x1 << (16 + RK312X_PLLS_MODE_OFFSET(id))))
+
+
#define RK312X_CRU_SOFTRST_CON 0x110
+#define RK312X_CRU_CLKSELS_CON_CNT (35)
+#define RK312X_CRU_CLKSELS_CON(i) (RK3036_CRU_CLKSEL_CON + ((i) * 4))
+
+#define RK312X_CRU_CLKGATES_CON_CNT (11)
+#define RK312X_CRU_CLKGATES_CON(i) (RK3036_CRU_CLKGATE_CON + ((i) * 4))
+
#define RK312X_CRU_SOFTRSTS_CON_CNT (9)
#define RK312X_CRU_SOFTRSTS_CON(i) (RK312X_CRU_SOFTRST_CON + ((i) * 4))
+/*******************CRU GATING*********************/
+#define RK312X_CRU_CONS_GATEID(i) (16 * (i))
+#define RK312X_CRU_GATEID_CONS(ID) (RK312X_CRU_CLKGATE_CON\
+ + ((ID) / 16) * 4)
+
+enum rk312x_cru_clk_gate {
+ /* SCU CLK GATE 0 CON */
+ RK312X_CLKGATE_UART0_SRC = (RK312X_CRU_CONS_GATEID(1) + 8),
+ RK312X_CLKGATE_PCLK_UART0 = (RK312X_CRU_CONS_GATEID(8) + 0),
+ RK312X_CLKGATE_PCLK_UART1,
+ RK312X_CLKGATE_PCLK_UART2,
+};
+
+/*************************RK3368********************************/
+
+/*******************CRU OFFSET*********************/
+#define RK3368_CRU_CLKSEL_CON 0x100
+#define RK3368_CRU_CLKGATE_CON 0x200
+#define RK3368_CRU_CLKGATES_CON_CNT 25
+
+#define RK3368_PLL_CONS(id, i) ((id) * 0x10 + ((i) * 4))
+#define RK3368_CRU_CLKSELS_CON(i) (RK3368_CRU_CLKSEL_CON + ((i) * 4))
+#define RK3368_CRU_CLKGATES_CON(i) (RK3368_CRU_CLKGATE_CON + ((i) * 4))
+
+#define RK3368_CRU_SOFTRSTS_CON_CNT (15)
+#define RK3368_CRU_SOFTRST_CON 0x300
+#define RK3368_CRU_SOFTRSTS_CON(i) (RK3368_CRU_SOFTRST_CON + ((i) * 4))
+
#endif