RK808_ID_SWITCH2,
};
+enum rk816_reg {
+ RK816_ID_DCDC1,
+ RK816_ID_DCDC2,
+ RK816_ID_DCDC3,
+ RK816_ID_DCDC4,
+ RK816_ID_BOOST = 5,
+ RK816_ID_OTG_SWITCH,
+ RK816_ID_LDO1 = 8,
+ RK816_ID_LDO2,
+ RK816_ID_LDO3,
+ RK816_ID_LDO4,
+ RK816_ID_LDO5,
+ RK816_ID_LDO6,
+};
+
enum rk818_reg {
RK818_ID_DCDC1,
RK818_ID_DCDC2,
#define RK805_PWRON_FALL_RISE_INT_EN 0x0
#define RK805_PWRON_FALL_RISE_INT_MSK 0x81
+/*VERSION REGISTER*/
+#define RK816_CHIP_NAME_REG 0x17
+#define RK816_CHIP_VER_REG 0x18
+#define RK816_OTP_VER_REG 0x19
+#define RK816_NUM_REGULATORS 12
+
+/*POWER ON/OFF REGISTER*/
+#define RK816_VB_MON_REG 0x21
+#define RK816_THERMAL_REG 0x22
+#define RK816_PWRON_LP_INT_TIME_REG 0x47
+#define RK816_PWRON_DB_REG 0x48
+#define RK816_DEV_CTRL_REG 0x4B
+#define RK816_ON_SOURCE_REG 0xAE
+#define RK816_OFF_SOURCE_REG 0xAF
+
+/*POWER CHANNELS ENABLE REGISTER*/
+#define RK816_DCDC_EN_REG1 0x23
+#define RK816_DCDC_EN_REG2 0x24
+#define RK816_SLP_DCDC_EN_REG 0x25
+#define RK816_SLP_LDO_EN_REG 0x26
+#define RK816_LDO_EN_REG1 0x27
+#define RK816_LDO_EN_REG2 0x28
+
+/*BUCK AND LDO CONFIG REGISTER*/
+#define RK816_BUCK1_CONFIG_REG 0x2E
+#define RK816_BUCK1_ON_VSEL_REG 0x2F
+#define RK816_BUCK1_SLP_VSEL_REG 0x30
+#define RK816_BUCK2_CONFIG_REG 0x32
+#define RK816_BUCK2_ON_VSEL_REG 0x33
+#define RK816_BUCK2_SLP_VSEL_REG 0x34
+#define RK816_BUCK3_CONFIG_REG 0x36
+#define RK816_BUCK4_CONFIG_REG 0x37
+#define RK816_BUCK4_ON_VSEL_REG 0x38
+#define RK816_BUCK4_SLP_VSEL_REG 0x39
+#define RK816_LDO1_ON_VSEL_REG 0x3B
+#define RK816_LDO1_SLP_VSEL_REG 0x3C
+#define RK816_LDO2_ON_VSEL_REG 0x3D
+#define RK816_LDO2_SLP_VSEL_REG 0x3E
+#define RK816_LDO3_ON_VSEL_REG 0x3F
+#define RK816_LDO3_SLP_VSEL_REG 0x40
+#define RK816_LDO4_ON_VSEL_REG 0x41
+#define RK816_LDO4_SLP_VSEL_REG 0x42
+#define RK816_LDO5_ON_VSEL_REG 0x43
+#define RK816_LDO5_SLP_VSEL_REG 0x44
+#define RK816_LDO6_ON_VSEL_REG 0x45
+#define RK816_LDO6_SLP_VSEL_REG 0x46
+
+/*CHARGER BOOST AND OTG REGISTER*/
+#define RK816_OTG_BUCK_LDO_CONFIG_REG 0x2A
+#define RK816_CHRG_CONFIG_REG 0x2B
+#define RK816_BOOST_ON_VESL_REG 0x54
+#define RK816_BOOST_SLP_VSEL_REG 0x55
+#define RK816_CHRG_BOOST_CONFIG_REG 0x9A
+#define RK816_SUP_STS_REG 0xA0
+#define RK816_USB_CTRL_REG 0xA1
+#define RK816_CHRG_CTRL_REG1 0xA3
+#define RK816_CHRG_CTRL_REG2 0xA4
+#define RK816_CHRG_CTRL_REG3 0xA5
+#define RK816_BAT_CTRL_REG 0xA6
+#define RK816_BAT_HTS_TS_REG 0xA8
+#define RK816_BAT_LTS_TS_REG 0xA9
+
+/*INTERRUPT REGISTER*/
+#define RK816_INT_STS_REG1 0x49
+#define RK816_INT_STS_MSK_REG1 0x4A
+#define RK816_INT_STS_REG2 0x4C
+#define RK816_INT_STS_MSK_REG2 0x4D
+#define RK816_INT_STS_REG3 0x4E
+#define RK816_INT_STS_MSK_REG3 0x4F
+#define RK816_GPIO_IO_POL_REG 0x50
+
+#define RK816_DATA18_REG 0xF2
+
+/* IRQ Definitions */
+#define RK816_IRQ_PWRON_FALL 0
+#define RK816_IRQ_PWRON_RISE 1
+#define RK816_IRQ_VB_LOW 2
+#define RK816_IRQ_PWRON 3
+#define RK816_IRQ_PWRON_LP 4
+#define RK816_IRQ_HOTDIE 5
+#define RK816_IRQ_RTC_ALARM 6
+#define RK816_IRQ_RTC_PERIOD 7
+#define RK816_IRQ_USB_OV 8
+#define RK816_IRQ_PLUG_IN 9
+#define RK816_IRQ_PLUG_OUT 10
+#define RK816_IRQ_CHG_OK 11
+#define RK816_IRQ_CHG_TE 12
+#define RK816_IRQ_CHG_TS 13
+#define RK816_IRQ_CHG_CVTLIM 14
+#define RK816_IRQ_DISCHG_ILIM 15
+
+#define RK816_IRQ_PWRON_FALL_MSK BIT(5)
+#define RK816_IRQ_PWRON_RISE_MSK BIT(6)
+#define RK816_IRQ_VB_LOW_MSK BIT(1)
+#define RK816_IRQ_PWRON_MSK BIT(2)
+#define RK816_IRQ_PWRON_LP_MSK BIT(3)
+#define RK816_IRQ_HOTDIE_MSK BIT(4)
+#define RK816_IRQ_RTC_ALARM_MSK BIT(5)
+#define RK816_IRQ_RTC_PERIOD_MSK BIT(6)
+#define RK816_IRQ_USB_OV_MSK BIT(7)
+#define RK816_IRQ_PLUG_IN_MSK BIT(0)
+#define RK816_IRQ_PLUG_OUT_MSK BIT(1)
+#define RK816_IRQ_CHG_OK_MSK BIT(2)
+#define RK816_IRQ_CHG_TE_MSK BIT(3)
+#define RK816_IRQ_CHG_TS_MSK BIT(4)
+#define RK816_IRQ_CHG_CVTLIM_MSK BIT(6)
+#define RK816_IRQ_DISCHG_ILIM_MSK BIT(7)
+
+#define RK816_VBAT_LOW_2V8 0x00
+#define RK816_VBAT_LOW_2V9 0x01
+#define RK816_VBAT_LOW_3V0 0x02
+#define RK816_VBAT_LOW_3V1 0x03
+#define RK816_VBAT_LOW_3V2 0x04
+#define RK816_VBAT_LOW_3V3 0x05
+#define RK816_VBAT_LOW_3V4 0x06
+#define RK816_VBAT_LOW_3V5 0x07
+#define RK816_PWR_FALL_INT_STATUS (0x1 << 5)
+#define RK816_PWR_RISE_INT_STATUS (0x1 << 6)
+#define RK816_ALARM_INT_STATUS (0x1 << 5)
+#define EN_VBAT_LOW_IRQ (0x1 << 4)
+#define VBAT_LOW_ACT_MASK (0x1 << 4)
+#define RTC_TIMER_ALARM_INT_MSK (0x3 << 2)
+#define RTC_TIMER_ALARM_INT_DIS (0x0 << 2)
+#define RTC_PERIOD_ALARM_INT_MSK (0x3 << 5)
+#define RTC_PERIOD_ALARM_INT_ST (0x3 << 5)
+#define RTC_PERIOD_ALARM_INT_DIS (0x3 << 5)
+#define RTC_PERIOD_ALARM_INT_EN (0x9f)
+#define REG_WRITE_MSK 0xff
+#define BUCK4_MAX_ILIMIT 0x2c
+#define BUCK_RATE_MSK (0x3 << 3)
+#define BUCK_RATE_12_5MV_US (0x2 << 3)
+#define ALL_INT_FLAGS_ST 0xff
+#define PLUGIN_OUT_INT_EN 0xfc
+#define RK816_PWRON_FALL_RISE_INT_EN 0x9f
+#define BUCK1_2_IMAX_MAX (0x3 << 6)
+#define BUCK3_4_IMAX_MAX (0x3 << 3)
+#define BOOST_DISABLE ((0x1 << 5) | (0x0 << 1))
+
+#define TEMP105C 0x08
#define TEMP115C 0x0c
#define TEMP_HOTDIE_MSK 0x0c
#define SLP_SD_MSK (0x3 << 2)
struct regmap_irq_chip_data *irq_data;
struct regmap *regmap;
long variant;
+ int hold_gpio;
+ int stby_gpio;
};
enum {
RK805_ID = 0x8050,
RK808_ID = 0x0000,
+ RK816_ID = 0x8160,
RK818_ID = 0x8180,
};
projects / firefly-linux-kernel-4.4.55.git / blobdiff