pd: rk3368: add rk3368 power domain support (as pd clk)

[firefly-linux-kernel-4.4.55.git] / include / dt-bindings / clock / rockchip.h

diff --git a/include/dt-bindings/clock/rockchip.h b/include/dt-bindings/clock/rockchip.h
index 7e4a970e4912709885c40ef4fb98314904406e40..4f8a6d4ea601378d78f7eda1855972d476cdbfd6 100644 (file)
--- a/include/dt-bindings/clock/rockchip.h
+++ b/include/dt-bindings/clock/rockchip.h
@@ -28,6 +28,10 @@
 #define CLK_IS_BASIC           BIT(5) /* Basic clk, can't do a to_clk_foo() */
 #define CLK_GET_RATE_NOCACHE   BIT(6) /* do not use the cached clk rate */
 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
+#define CLK_SET_RATE_PARENT_IN_ORDER BIT(8) /* consider the order of re-parent
+                                               and set_div on rate change */
+
+
 
 /* Rockchip pll flags */
 #define CLK_PLL_3188           BIT(0)
@@ -35,6 +39,14 @@
 #define CLK_PLL_3188PLUS       BIT(2)
 #define CLK_PLL_3188PLUS_APLL  BIT(3)
 #define CLK_PLL_3288_APLL      BIT(4)
+#define CLK_PLL_3188PLUS_AUTO  BIT(5)
+#define CLK_PLL_3036_APLL      BIT(6)
+#define CLK_PLL_3036PLUS_AUTO  BIT(7)
+#define CLK_PLL_312XPLUS       BIT(8)
+#define CLK_PLL_3368_APLLB     BIT(9)
+#define CLK_PLL_3368_APLLL     BIT(10)
+#define CLK_PLL_3368_LOW_JITTER        BIT(11)
+
 
 /* rate_ops index */
 #define CLKOPS_RATE_MUX_DIV            1
@@ -51,6 +63,14 @@
 #define CLKOPS_RATE_CORE_CHILD         12
 #define CLKOPS_RATE_DDR                        13
 #define CLKOPS_RATE_RK3288_I2S         14
+#define CLKOPS_RATE_RK3288_USB480M     15
+#define CLKOPS_RATE_RK3288_DCLK_LCDC0  16
+#define CLKOPS_RATE_RK3288_DCLK_LCDC1  17
+#define CLKOPS_RATE_DDR_DIV2           18
+#define CLKOPS_RATE_DDR_DIV4           19
+#define CLKOPS_RATE_RK3368_MUX_DIV_NPLL 20
+#define CLKOPS_RATE_RK3368_DCLK_LCDC   21
+
 #define CLKOPS_TABLE_END               (~0)
 
 /* pd id */
@@ -68,6 +88,12 @@
 #define CLK_PD_SCU             11
 #define CLK_PD_VIDEO           12
 #define CLK_PD_VIO             13
+#define CLK_PD_GPU_0           14
+#define CLK_PD_GPU_1           15
+
+#define CLK_PD_VIRT            255
 
+/* reset flag */
+#define ROCKCHIP_RESET_HIWORD_MASK     BIT(0)
 
 #endif /* _DT_BINDINGS_CLOCK_ROCKCHIP_H */