video/rockchip: rga2 support dma fd

[firefly-linux-kernel-4.4.55.git] / drivers / video / rockchip / rga2 / rga2_reg_info.c

diff --git a/drivers/video/rockchip/rga2/rga2_reg_info.c b/drivers/video/rockchip/rga2/rga2_reg_info.c
index 06d0df818bd96608b5206e18a6b4cf82bd49bc75..81b94569ef236307dd3d5fa1176ebb1a5d8d55bb 100755 (executable)
--- a/drivers/video/rockchip/rga2/rga2_reg_info.c
+++ b/drivers/video/rockchip/rga2/rga2_reg_info.c
@@ -75,7 +75,7 @@ RGA2_reg_get_param(unsigned char *base, struct rga2_req *msg)
     {\r
         x_flag = 1;\r
         #if SCALE_DOWN_LARGE\r
-        param_x = ((dw) << 16) / (sw);\r
+        param_x = ((dw) << 16) / (sw) + 1;\r
                #else\r
         param_x = ((dw) << 16) / (sw);\r
         #endif\r
@@ -100,7 +100,7 @@ RGA2_reg_get_param(unsigned char *base, struct rga2_req *msg)
     {\r
         y_flag = 1;\r
         #if SCALE_DOWN_LARGE\r
-        param_y = ((dh) << 16) / (sh);\r
+        param_y = ((dh) << 16) / (sh) + 1;\r
                #else\r
         param_y = ((dh) << 16) / (sh);\r
         #endif\r
@@ -171,6 +171,7 @@ RGA2_set_reg_src_info(RK_U8 *base, struct rga2_req *msg)
     RK_U32 uv_stride = 0;\r
     RK_U32 mask_stride = 0;\r
     RK_U32 ydiv = 1, xdiv = 2;\r
+    RK_U8  yuv10 = 0;\r
 \r
     RK_U32 sw, sh;\r
     RK_U32 dw, dh;\r
@@ -191,6 +192,14 @@ RGA2_set_reg_src_info(RK_U8 *base, struct rga2_req *msg)
     bRGA_SRC_TR_COLOR0 = (RK_U32 *)(base + RGA2_SRC_TR_COLOR0_OFFSET);\r
     bRGA_SRC_TR_COLOR1 = (RK_U32 *)(base + RGA2_SRC_TR_COLOR1_OFFSET);\r
 \r
+    if (msg->src.format == RGA2_FORMAT_YCbCr_420_SP_10B ||\r
+        msg->src.format == RGA2_FORMAT_YCrCb_420_SP_10B) {\r
+       if ((msg->src.act_w == msg->dst.act_w) &&\r
+           (msg->src.act_h == msg->dst.act_h) &&\r
+           (msg->rotate_mode == 0))\r
+           msg->rotate_mode = 1 << 6;\r
+    }\r
+\r
     {\r
         rotate_mode = msg->rotate_mode & 0x3;\r
 \r
@@ -252,6 +261,8 @@ RGA2_set_reg_src_info(RK_U8 *base, struct rga2_req *msg)
         case RGA2_FORMAT_YCrCb_422_P  : src0_format = 0x9; xdiv = 2; ydiv = 1; src0_cbcr_swp = 1; break;\r
         case RGA2_FORMAT_YCrCb_420_SP : src0_format = 0xa; xdiv = 1; ydiv = 2; src0_cbcr_swp = 1; break;\r
         case RGA2_FORMAT_YCrCb_420_P  : src0_format = 0xb; xdiv = 2; ydiv = 2; src0_cbcr_swp = 1; break;\r
+        case RGA2_FORMAT_YCbCr_420_SP_10B : src0_format = 0xa; xdiv = 1; ydiv = 2; yuv10 = 1; break;\r
+        case RGA2_FORMAT_YCrCb_420_SP_10B : src0_format = 0xa; xdiv = 1; ydiv = 2; src0_cbcr_swp = 1; yuv10 = 1; break;\r
     };\r
 \r
     reg = ((reg & (~m_RGA2_SRC_INFO_SW_SRC_FMT)) | (s_RGA2_SRC_INFO_SW_SRC_FMT(src0_format)));\r
@@ -275,10 +286,11 @@ RGA2_set_reg_src_info(RK_U8 *base, struct rga2_req *msg)
     reg = ((reg & (~m_RGA2_SRC_INFO_SW_SW_SRC_TRANS_E)) | (s_RGA2_SRC_INFO_SW_SW_SRC_TRANS_E(msg->src_trans_mode >> 1)));\r
     reg = ((reg & (~m_RGA2_SRC_INFO_SW_SW_SRC_DITHER_UP_E)) | (s_RGA2_SRC_INFO_SW_SW_SRC_DITHER_UP_E((msg->alpha_rop_flag >> 4) & 0x1)));\r
     reg = ((reg & (~m_RGA2_SRC_INFO_SW_SW_VSP_MODE_SEL)) | (s_RGA2_SRC_INFO_SW_SW_VSP_MODE_SEL((msg->scale_bicu_mode>>4))));\r
+    reg = ((reg & (~m_RGA2_SRC_INFO_SW_SW_YUV10_E)) | (s_RGA2_SRC_INFO_SW_SW_YUV10_E((yuv10))));\r
+    reg = ((reg & (~m_RGA2_SRC_INFO_SW_SW_YUV10_ROUND_E)) | (s_RGA2_SRC_INFO_SW_SW_YUV10_ROUND_E((yuv10))));\r
     RGA2_reg_get_param(base, msg);\r
 \r
     stride = (((msg->src.vir_w * pixel_width) + 3) & ~3) >> 2;\r
-\r
     uv_stride = ((msg->src.vir_w / xdiv + 3) & ~3);\r
 \r
     *bRGA_SRC_BASE0 = (RK_U32)(msg->src.yrgb_addr + msg->src.y_offset * (stride<<2) + msg->src.x_offset * pixel_width);\r
@@ -679,7 +691,7 @@ RGA2_set_reg_color_palette(RK_U8 *base, struct rga2_req *msg)
 \r
     src_stride = (byte_num + 3) & (~3);\r
 \r
-    p = (RK_U32 *)msg->src.yrgb_addr;\r
+    p = (RK_U32 *)((unsigned long)msg->src.yrgb_addr);\r
 \r
     #if 0\r
     if(endian_mode)\r
@@ -961,13 +973,21 @@ void format_name_convert(uint32_t *df, uint32_t sf)
         case 0xd: *df = RGA2_FORMAT_YCrCb_422_P; break;\r
         case 0xe: *df = RGA2_FORMAT_YCrCb_420_SP; break;\r
         case 0xf: *df = RGA2_FORMAT_YCrCb_420_P; break;\r
+\r
+        case 0x20:*df = RGA2_FORMAT_YCbCr_420_SP_10B; break;\r
+        case 0x21:*df = RGA2_FORMAT_YCrCb_420_SP_10B; break;\r
     }\r
 }\r
 \r
 void RGA_MSG_2_RGA2_MSG(struct rga_req *req_rga, struct rga2_req *req)\r
-{\r
-    u16 alpha_mode_0, alpha_mode_1;\r
-\r
+{
+       u16 alpha_mode_0, alpha_mode_1;
+
+       if (req_rga->render_mode & RGA_BUF_GEM_TYPE_MASK)
+               req->buf_type = RGA_BUF_GEM_TYPE_MASK & RGA_BUF_GEM_TYPE_DMA;
+
+       req_rga->render_mode &= (~RGA_BUF_GEM_TYPE_MASK);
+
     if (req_rga->render_mode == 6)\r
         req->render_mode = update_palette_table_mode;\r
     else if (req_rga->render_mode == 7)\r
@@ -1014,12 +1034,12 @@ void RGA_MSG_2_RGA2_MSG(struct rga_req *req_rga, struct rga2_req *req)
     else if (req_rga->rotate_mode == 2)\r
     {\r
         //x_mirror\r
-        req->rotate_mode = (1 << 4);\r
+        req->rotate_mode |= (1 << 4);\r
     }\r
     else if (req_rga->rotate_mode == 3)\r
     {\r
         //y_mirror\r
-        req->rotate_mode = (2 << 4);\r
+        req->rotate_mode |= (2 << 4);\r
     }\r
     else {\r
         req->rotate_mode = 0;\r
@@ -1034,7 +1054,7 @@ void RGA_MSG_2_RGA2_MSG(struct rga_req *req_rga, struct rga2_req *req)
     req->bitblt_mode = req_rga->bsfilter_flag;\r
 \r
     req->src_a_global_val = req_rga->alpha_global_value;\r
-    req->dst_a_global_val = 0;\r
+    req->dst_a_global_val = req_rga->alpha_global_value;\r
     req->rop_code = req_rga->rop_code;\r
     req->rop_mode = 0;\r
 \r
@@ -1065,10 +1085,10 @@ void RGA_MSG_2_RGA2_MSG(struct rga_req *req_rga, struct rga2_req *req)
     req->alpha_rop_flag |= (((req_rga->alpha_rop_flag >> 5) & 1) << 6); // dst_dither_down\r
     req->alpha_rop_flag |= (((req_rga->alpha_rop_flag >> 6) & 1) << 7); // gradient fill mode sel\r
 \r
-    if(((req_rga->alpha_rop_flag) & 1)) {\r
-        if((req_rga->alpha_rop_flag >> 3) & 1) {\r
+    if (((req_rga->alpha_rop_flag) & 1)) {\r
+        if ((req_rga->alpha_rop_flag >> 3) & 1) {\r
             /* porter duff alpha enable */\r
-            switch(req_rga->PD_mode)\r
+            switch (req_rga->PD_mode)\r
             {\r
                 case 0: //dst = 0\r
                     break;\r
@@ -1114,6 +1134,10 @@ void RGA_MSG_2_RGA2_MSG(struct rga_req *req_rga, struct rga2_req *req)
                     break;\r
                 case 11://dst = ((256-da)*sc + (256-sa)*dc) >> 8;\r
                     break;\r
+               case 12:\r
+                   req->alpha_mode_0 = 0x0010;\r
+                   req->alpha_mode_1 = 0x0820;\r
+                   break;\r
                 default:\r
                     break;\r
             }\r
@@ -1178,8 +1202,14 @@ void memcpy_img_info(struct rga_img_info_t *dst, struct rga_img_info_32_t *src)
     dst->alpha_swap = src->alpha_swap;\r
 }\r
 void RGA_MSG_2_RGA2_MSG_32(struct rga_req_32 *req_rga, struct rga2_req *req)\r
-{\r
-    u16 alpha_mode_0, alpha_mode_1;\r
+{
+       u16 alpha_mode_0, alpha_mode_1;
+
+       if (req_rga->render_mode & RGA_BUF_GEM_TYPE_MASK)
+               req->buf_type = RGA_BUF_GEM_TYPE_MASK & RGA_BUF_GEM_TYPE_DMA;
+
+       req_rga->render_mode &= (~RGA_BUF_GEM_TYPE_MASK);
+
     if (req_rga->render_mode == 6)\r
         req->render_mode = update_palette_table_mode;\r
     else if (req_rga->render_mode == 7)\r
@@ -1233,7 +1263,7 @@ void RGA_MSG_2_RGA2_MSG_32(struct rga_req_32 *req_rga, struct rga2_req *req)
     req->rop_mask_addr = req_rga->rop_mask_addr;\r
     req->bitblt_mode = req_rga->bsfilter_flag;\r
     req->src_a_global_val = req_rga->alpha_global_value;\r
-    req->dst_a_global_val = 0;\r
+    req->dst_a_global_val = req_rga->alpha_global_value;\r
     req->rop_code = req_rga->rop_code;\r
     req->rop_mode = 0;\r
     req->color_fill_mode = req_rga->color_fill_mode;\r
@@ -1305,6 +1335,10 @@ void RGA_MSG_2_RGA2_MSG_32(struct rga_req_32 *req_rga, struct rga2_req *req)
                     break;\r
                 case 11://dst = ((256-da)*sc + (256-sa)*dc) >> 8;\r
                     break;\r
+               case 12:\r
+                   req->alpha_mode_0 = 0x0010;\r
+                   req->alpha_mode_1 = 0x0820;\r
+                   break;\r
                 default:\r
                     break;\r
             }\r