rockchip/rga: add rga support yuv 10 bit

[firefly-linux-kernel-4.4.55.git] / drivers / video / rockchip / rga2 / rga2_reg_info.c

diff --git a/drivers/video/rockchip/rga2/rga2_reg_info.c b/drivers/video/rockchip/rga2/rga2_reg_info.c
index 91667416f340e27d14a5b2d817326c1009c793a7..7d8a4d676f7fa560a1334e909f6b152b25c93d07 100755 (executable)
--- a/drivers/video/rockchip/rga2/rga2_reg_info.c
+++ b/drivers/video/rockchip/rga2/rga2_reg_info.c
@@ -171,6 +171,7 @@ RGA2_set_reg_src_info(RK_U8 *base, struct rga2_req *msg)
     RK_U32 uv_stride = 0;\r
     RK_U32 mask_stride = 0;\r
     RK_U32 ydiv = 1, xdiv = 2;\r
+    RK_U8  yuv10 = 0;\r
 \r
     RK_U32 sw, sh;\r
     RK_U32 dw, dh;\r
@@ -191,6 +192,14 @@ RGA2_set_reg_src_info(RK_U8 *base, struct rga2_req *msg)
     bRGA_SRC_TR_COLOR0 = (RK_U32 *)(base + RGA2_SRC_TR_COLOR0_OFFSET);\r
     bRGA_SRC_TR_COLOR1 = (RK_U32 *)(base + RGA2_SRC_TR_COLOR1_OFFSET);\r
 \r
+    if (msg->src.format == RGA2_FORMAT_YCbCr_420_SP_10B ||\r
+        msg->src.format == RGA2_FORMAT_YCrCb_420_SP_10B) {\r
+       if ((msg->src.act_w == msg->dst.act_w) &&\r
+           (msg->src.act_h == msg->dst.act_h) &&\r
+           (msg->rotate_mode == 0))\r
+           msg->rotate_mode = 1 << 6;\r
+    }\r
+\r
     {\r
         rotate_mode = msg->rotate_mode & 0x3;\r
 \r
@@ -252,6 +261,8 @@ RGA2_set_reg_src_info(RK_U8 *base, struct rga2_req *msg)
         case RGA2_FORMAT_YCrCb_422_P  : src0_format = 0x9; xdiv = 2; ydiv = 1; src0_cbcr_swp = 1; break;\r
         case RGA2_FORMAT_YCrCb_420_SP : src0_format = 0xa; xdiv = 1; ydiv = 2; src0_cbcr_swp = 1; break;\r
         case RGA2_FORMAT_YCrCb_420_P  : src0_format = 0xb; xdiv = 2; ydiv = 2; src0_cbcr_swp = 1; break;\r
+        case RGA2_FORMAT_YCbCr_420_SP_10B : src0_format = 0xa; xdiv = 1; ydiv = 2; yuv10 = 1; break;\r
+        case RGA2_FORMAT_YCrCb_420_SP_10B : src0_format = 0xa; xdiv = 1; ydiv = 2; src0_cbcr_swp = 1; yuv10 = 1; break;\r
     };\r
 \r
     reg = ((reg & (~m_RGA2_SRC_INFO_SW_SRC_FMT)) | (s_RGA2_SRC_INFO_SW_SRC_FMT(src0_format)));\r
@@ -275,10 +286,11 @@ RGA2_set_reg_src_info(RK_U8 *base, struct rga2_req *msg)
     reg = ((reg & (~m_RGA2_SRC_INFO_SW_SW_SRC_TRANS_E)) | (s_RGA2_SRC_INFO_SW_SW_SRC_TRANS_E(msg->src_trans_mode >> 1)));\r
     reg = ((reg & (~m_RGA2_SRC_INFO_SW_SW_SRC_DITHER_UP_E)) | (s_RGA2_SRC_INFO_SW_SW_SRC_DITHER_UP_E((msg->alpha_rop_flag >> 4) & 0x1)));\r
     reg = ((reg & (~m_RGA2_SRC_INFO_SW_SW_VSP_MODE_SEL)) | (s_RGA2_SRC_INFO_SW_SW_VSP_MODE_SEL((msg->scale_bicu_mode>>4))));\r
+    reg = ((reg & (~m_RGA2_SRC_INFO_SW_SW_YUV10_E)) | (s_RGA2_SRC_INFO_SW_SW_YUV10_E((yuv10))));\r
+    reg = ((reg & (~m_RGA2_SRC_INFO_SW_SW_YUV10_ROUND_E)) | (s_RGA2_SRC_INFO_SW_SW_YUV10_ROUND_E((yuv10))));\r
     RGA2_reg_get_param(base, msg);\r
 \r
     stride = (((msg->src.vir_w * pixel_width) + 3) & ~3) >> 2;\r
-\r
     uv_stride = ((msg->src.vir_w / xdiv + 3) & ~3);\r
 \r
     *bRGA_SRC_BASE0 = (RK_U32)(msg->src.yrgb_addr + msg->src.y_offset * (stride<<2) + msg->src.x_offset * pixel_width);\r
@@ -961,6 +973,9 @@ void format_name_convert(uint32_t *df, uint32_t sf)
         case 0xd: *df = RGA2_FORMAT_YCrCb_422_P; break;\r
         case 0xe: *df = RGA2_FORMAT_YCrCb_420_SP; break;\r
         case 0xf: *df = RGA2_FORMAT_YCrCb_420_P; break;\r
+\r
+        case 0x20:*df = RGA2_FORMAT_YCbCr_420_SP_10B; break;\r
+        case 0x21:*df = RGA2_FORMAT_YCrCb_420_SP_10B; break;\r
     }\r
 }\r
 \r
@@ -1014,12 +1029,12 @@ void RGA_MSG_2_RGA2_MSG(struct rga_req *req_rga, struct rga2_req *req)
     else if (req_rga->rotate_mode == 2)\r
     {\r
         //x_mirror\r
-        req->rotate_mode = (1 << 4);\r
+        req->rotate_mode |= (1 << 4);\r
     }\r
     else if (req_rga->rotate_mode == 3)\r
     {\r
         //y_mirror\r
-        req->rotate_mode = (2 << 4);\r
+        req->rotate_mode |= (2 << 4);\r
     }\r
     else {\r
         req->rotate_mode = 0;\r