/*
- * rockchip spi interface driver for DW SPI Core
- *
- * Copyright (c) 2014, ROCKCHIP Corporation.
+ * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
+ * Author: Addy Ke <addy.ke@rock-chips.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation,
- * Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
*/
-#include <linux/interrupt.h>
-#include <linux/slab.h>
#include <linux/init.h>
#include <linux/module.h>
-#include <linux/workqueue.h>
-#include <linux/interrupt.h>
-#include <linux/delay.h>
#include <linux/clk.h>
-#include <linux/dma-mapping.h>
-#include <linux/dmaengine.h>
+#include <linux/err.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
#include <linux/platform_device.h>
-#include <linux/pm_runtime.h>
+#include <linux/slab.h>
#include <linux/spi/spi.h>
-#include <linux/gpio.h>
+#include <linux/scatterlist.h>
#include <linux/of.h>
-#include <linux/of_gpio.h>
-#include <linux/platform_data/spi-rockchip.h>
-
-#include "spi-rockchip-core.h"
+#include <linux/pm_runtime.h>
+#include <linux/io.h>
+#include <linux/dmaengine.h>
+#define DRIVER_NAME "rockchip-spi"
+
+/* SPI register offsets */
+#define ROCKCHIP_SPI_CTRLR0 0x0000
+#define ROCKCHIP_SPI_CTRLR1 0x0004
+#define ROCKCHIP_SPI_SSIENR 0x0008
+#define ROCKCHIP_SPI_SER 0x000c
+#define ROCKCHIP_SPI_BAUDR 0x0010
+#define ROCKCHIP_SPI_TXFTLR 0x0014
+#define ROCKCHIP_SPI_RXFTLR 0x0018
+#define ROCKCHIP_SPI_TXFLR 0x001c
+#define ROCKCHIP_SPI_RXFLR 0x0020
+#define ROCKCHIP_SPI_SR 0x0024
+#define ROCKCHIP_SPI_IPR 0x0028
+#define ROCKCHIP_SPI_IMR 0x002c
+#define ROCKCHIP_SPI_ISR 0x0030
+#define ROCKCHIP_SPI_RISR 0x0034
+#define ROCKCHIP_SPI_ICR 0x0038
+#define ROCKCHIP_SPI_DMACR 0x003c
+#define ROCKCHIP_SPI_DMATDLR 0x0040
+#define ROCKCHIP_SPI_DMARDLR 0x0044
+#define ROCKCHIP_SPI_TXDR 0x0400
+#define ROCKCHIP_SPI_RXDR 0x0800
+
+/* Bit fields in CTRLR0 */
+#define CR0_DFS_OFFSET 0
+
+#define CR0_CFS_OFFSET 2
+
+#define CR0_SCPH_OFFSET 6
+
+#define CR0_SCPOL_OFFSET 7
+
+#define CR0_CSM_OFFSET 8
+#define CR0_CSM_KEEP 0x0
+/* ss_n be high for half sclk_out cycles */
+#define CR0_CSM_HALF 0X1
+/* ss_n be high for one sclk_out cycle */
+#define CR0_CSM_ONE 0x2
+
+/* ss_n to sclk_out delay */
+#define CR0_SSD_OFFSET 10
+/*
+ * The period between ss_n active and
+ * sclk_out active is half sclk_out cycles
+ */
+#define CR0_SSD_HALF 0x0
+/*
+ * The period between ss_n active and
+ * sclk_out active is one sclk_out cycle
+ */
+#define CR0_SSD_ONE 0x1
+
+#define CR0_EM_OFFSET 11
+#define CR0_EM_LITTLE 0x0
+#define CR0_EM_BIG 0x1
+
+#define CR0_FBM_OFFSET 12
+#define CR0_FBM_MSB 0x0
+#define CR0_FBM_LSB 0x1
+
+#define CR0_BHT_OFFSET 13
+#define CR0_BHT_16BIT 0x0
+#define CR0_BHT_8BIT 0x1
+
+#define CR0_RSD_OFFSET 14
+
+#define CR0_FRF_OFFSET 16
+#define CR0_FRF_SPI 0x0
+#define CR0_FRF_SSP 0x1
+#define CR0_FRF_MICROWIRE 0x2
+
+#define CR0_XFM_OFFSET 18
+#define CR0_XFM_MASK (0x03 << SPI_XFM_OFFSET)
+#define CR0_XFM_TR 0x0
+#define CR0_XFM_TO 0x1
+#define CR0_XFM_RO 0x2
+
+#define CR0_OPM_OFFSET 20
+#define CR0_OPM_MASTER 0x0
+#define CR0_OPM_SLAVE 0x1
+
+#define CR0_MTM_OFFSET 0x21
+
+/* Bit fields in SER, 2bit */
+#define SER_MASK 0x3
+
+/* Bit fields in SR, 5bit */
+#define SR_MASK 0x1f
+#define SR_BUSY (1 << 0)
+#define SR_TF_FULL (1 << 1)
+#define SR_TF_EMPTY (1 << 2)
+#define SR_RF_EMPTY (1 << 3)
+#define SR_RF_FULL (1 << 4)
+
+/* Bit fields in ISR, IMR, ISR, RISR, 5bit */
+#define INT_MASK 0x1f
+#define INT_TF_EMPTY (1 << 0)
+#define INT_TF_OVERFLOW (1 << 1)
+#define INT_RF_UNDERFLOW (1 << 2)
+#define INT_RF_OVERFLOW (1 << 3)
+#define INT_RF_FULL (1 << 4)
+
+/* Bit fields in ICR, 4bit */
+#define ICR_MASK 0x0f
+#define ICR_ALL (1 << 0)
+#define ICR_RF_UNDERFLOW (1 << 1)
+#define ICR_RF_OVERFLOW (1 << 2)
+#define ICR_TF_OVERFLOW (1 << 3)
+
+/* Bit fields in DMACR */
+#define RF_DMA_EN (1 << 0)
+#define TF_DMA_EN (1 << 1)
+
+#define RXBUSY (1 << 0)
+#define TXBUSY (1 << 1)
+
+/* sclk_out: spi master internal logic in rk3x can support 50Mhz */
+#define MAX_SCLK_OUT 50000000
+
+enum rockchip_ssi_type {
+ SSI_MOTO_SPI = 0,
+ SSI_TI_SSP,
+ SSI_NS_MICROWIRE,
+};
-#define DRIVER_NAME "rockchip_spi_driver_data"
-#define SPI_MAX_FREQUENCY 24000000
+struct rockchip_spi_dma_data {
+ struct dma_chan *ch;
+ enum dma_transfer_direction direction;
+ dma_addr_t addr;
+};
-struct rockchip_spi_driver_data {
- struct platform_device *pdev;
- struct dw_spi dws;
- struct rockchip_spi_info *info;
- struct clk *clk_spi;
- struct clk *pclk_spi;
+struct rockchip_spi {
+ struct device *dev;
+ struct spi_master *master;
+
+ struct clk *spiclk;
+ struct clk *apb_pclk;
+
+ void __iomem *regs;
+ /*depth of the FIFO buffer */
+ u32 fifo_len;
+ /* max bus freq supported */
+ u32 max_freq;
+ /* supported slave numbers */
+ enum rockchip_ssi_type type;
+
+ u16 mode;
+ u8 tmode;
+ u8 bpw;
+ u8 n_bytes;
+ u8 rsd_nsecs;
+ unsigned len;
+ u32 speed;
+
+ const void *tx;
+ const void *tx_end;
+ void *rx;
+ void *rx_end;
+
+ u32 state;
+ /* protect state */
+ spinlock_t lock;
+
+ u32 use_dma;
+ struct sg_table tx_sg;
+ struct sg_table rx_sg;
+ struct rockchip_spi_dma_data dma_rx;
+ struct rockchip_spi_dma_data dma_tx;
};
-#ifdef CONFIG_OF
-static struct rockchip_spi_info *rockchip_spi_parse_dt(struct device *dev)
+static inline void spi_enable_chip(struct rockchip_spi *rs, int enable)
{
- struct rockchip_spi_info *info;
- u32 temp;
+ writel_relaxed((enable ? 1 : 0), rs->regs + ROCKCHIP_SPI_SSIENR);
+}
- info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
- if (!info) {
- dev_err(dev, "memory allocation for spi_info failed\n");
- return ERR_PTR(-ENOMEM);
- }
+static inline void spi_set_clk(struct rockchip_spi *rs, u16 div)
+{
+ writel_relaxed(div, rs->regs + ROCKCHIP_SPI_BAUDR);
+}
- if (of_property_read_u32(dev->of_node, "rockchip,spi-src-clk", &temp)) {
- dev_warn(dev, "spi bus clock parent not specified, using clock at index 0 as parent\n");
- info->src_clk_nr = 0;
- } else {
- info->src_clk_nr = temp;
+static inline void flush_fifo(struct rockchip_spi *rs)
+{
+ while (readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR))
+ readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR);
+}
+
+static inline void wait_for_idle(struct rockchip_spi *rs)
+{
+ unsigned long timeout = jiffies + msecs_to_jiffies(5);
+
+ do {
+ if (!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY))
+ return;
+ } while (!time_after(jiffies, timeout));
+
+ dev_warn(rs->dev, "spi controller is in busy state!\n");
+}
+
+static u32 get_fifo_len(struct rockchip_spi *rs)
+{
+ u32 fifo;
+
+ for (fifo = 2; fifo < 32; fifo++) {
+ writel_relaxed(fifo, rs->regs + ROCKCHIP_SPI_TXFTLR);
+ if (fifo != readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFTLR))
+ break;
}
-#if 0
- if (of_property_read_u32(dev->of_node, "bus-num", &temp)) {
- dev_warn(dev, "number of bus not specified, assuming bus 0\n");
- info->bus_num= 0;
- } else {
- info->bus_num = temp;
+
+ writel_relaxed(0, rs->regs + ROCKCHIP_SPI_TXFTLR);
+
+ return (fifo == 31) ? 0 : fifo;
+}
+
+static inline u32 tx_max(struct rockchip_spi *rs)
+{
+ u32 tx_left, tx_room;
+
+ tx_left = (rs->tx_end - rs->tx) / rs->n_bytes;
+ tx_room = rs->fifo_len - readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFLR);
+
+ return min(tx_left, tx_room);
+}
+
+static inline u32 rx_max(struct rockchip_spi *rs)
+{
+ u32 rx_left = (rs->rx_end - rs->rx) / rs->n_bytes;
+ u32 rx_room = (u32)readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR);
+
+ return min(rx_left, rx_room);
+}
+
+static void rockchip_spi_set_cs(struct spi_device *spi, bool enable)
+{
+ u32 ser;
+ struct spi_master *master = spi->master;
+ struct rockchip_spi *rs = spi_master_get_devdata(master);
+
+ pm_runtime_get_sync(rs->dev);
+
+ ser = readl_relaxed(rs->regs + ROCKCHIP_SPI_SER) & SER_MASK;
+
+ /*
+ * drivers/spi/spi.c:
+ * static void spi_set_cs(struct spi_device *spi, bool enable)
+ * {
+ * if (spi->mode & SPI_CS_HIGH)
+ * enable = !enable;
+ *
+ * if (spi->cs_gpio >= 0)
+ * gpio_set_value(spi->cs_gpio, !enable);
+ * else if (spi->master->set_cs)
+ * spi->master->set_cs(spi, !enable);
+ * }
+ *
+ * Note: enable(rockchip_spi_set_cs) = !enable(spi_set_cs)
+ */
+ if (!enable)
+ ser |= 1 << spi->chip_select;
+ else
+ ser &= ~(1 << spi->chip_select);
+
+ writel_relaxed(ser, rs->regs + ROCKCHIP_SPI_SER);
+
+ pm_runtime_put_sync(rs->dev);
+}
+
+static int rockchip_spi_prepare_message(struct spi_master *master,
+ struct spi_message *msg)
+{
+ struct rockchip_spi *rs = spi_master_get_devdata(master);
+ struct spi_device *spi = msg->spi;
+
+ rs->mode = spi->mode;
+
+ return 0;
+}
+
+static void rockchip_spi_handle_err(struct spi_master *master,
+ struct spi_message *msg)
+{
+ unsigned long flags;
+ struct rockchip_spi *rs = spi_master_get_devdata(master);
+
+ spin_lock_irqsave(&rs->lock, flags);
+
+ /*
+ * For DMA mode, we need terminate DMA channel and flush
+ * fifo for the next transfer if DMA thansfer timeout.
+ * handle_err() was called by core if transfer failed.
+ * Maybe it is reasonable for error handling here.
+ */
+ if (rs->use_dma) {
+ if (rs->state & RXBUSY) {
+ dmaengine_terminate_all(rs->dma_rx.ch);
+ flush_fifo(rs);
+ }
+
+ if (rs->state & TXBUSY)
+ dmaengine_terminate_all(rs->dma_tx.ch);
}
-#endif
- if (of_property_read_u32(dev->of_node, "num-cs", &temp)) {
- dev_warn(dev, "number of chip select lines not specified, assuming 1 chip select line\n");
- info->num_cs = 1;
- } else {
- info->num_cs = temp;
+
+ spin_unlock_irqrestore(&rs->lock, flags);
+}
+
+static int rockchip_spi_unprepare_message(struct spi_master *master,
+ struct spi_message *msg)
+{
+ struct rockchip_spi *rs = spi_master_get_devdata(master);
+
+ spi_enable_chip(rs, 0);
+
+ return 0;
+}
+
+static void rockchip_spi_pio_writer(struct rockchip_spi *rs)
+{
+ u32 max = tx_max(rs);
+ u32 txw = 0;
+
+ while (max--) {
+ if (rs->n_bytes == 1)
+ txw = *(u8 *)(rs->tx);
+ else
+ txw = *(u16 *)(rs->tx);
+
+ writel_relaxed(txw, rs->regs + ROCKCHIP_SPI_TXDR);
+ rs->tx += rs->n_bytes;
}
+}
- if (of_property_read_u32(dev->of_node, "max-freq", &temp)) {
- dev_warn(dev, "fail to get max-freq,default set %dHZ\n",SPI_MAX_FREQUENCY);
- info->spi_freq = SPI_MAX_FREQUENCY;
- } else {
- info->spi_freq = temp;
+static void rockchip_spi_pio_reader(struct rockchip_spi *rs)
+{
+ u32 max = rx_max(rs);
+ u32 rxw;
+
+ while (max--) {
+ rxw = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR);
+ if (rs->n_bytes == 1)
+ *(u8 *)(rs->rx) = (u8)rxw;
+ else
+ *(u16 *)(rs->rx) = (u16)rxw;
+ rs->rx += rs->n_bytes;
}
-
- //printk("%s:line=%d,src_clk_nr=%d,bus_num=%d,num_cs=%d\n",__func__, __LINE__,info->src_clk_nr,info->bus_num,info->num_cs);
-
- return info;
}
-#else
-static struct rockchip_spi_info *rockchip_spi_parse_dt(struct device *dev)
+
+static int rockchip_spi_pio_transfer(struct rockchip_spi *rs)
{
- return dev->platform_data;
+ int remain = 0;
+
+ do {
+ if (rs->tx) {
+ remain = rs->tx_end - rs->tx;
+ rockchip_spi_pio_writer(rs);
+ }
+
+ if (rs->rx) {
+ remain = rs->rx_end - rs->rx;
+ rockchip_spi_pio_reader(rs);
+ }
+
+ cpu_relax();
+ } while (remain);
+
+ /* If tx, wait until the FIFO data completely. */
+ if (rs->tx)
+ wait_for_idle(rs);
+
+ spi_enable_chip(rs, 0);
+
+ return 0;
}
-#endif
+static void rockchip_spi_dma_rxcb(void *data)
+{
+ unsigned long flags;
+ struct rockchip_spi *rs = data;
-static int rockchip_spi_probe(struct platform_device *pdev)
+ spin_lock_irqsave(&rs->lock, flags);
+
+ rs->state &= ~RXBUSY;
+ if (!(rs->state & TXBUSY)) {
+ spi_enable_chip(rs, 0);
+ spi_finalize_current_transfer(rs->master);
+ }
+
+ spin_unlock_irqrestore(&rs->lock, flags);
+}
+
+static void rockchip_spi_dma_txcb(void *data)
{
- struct resource *mem_res;
- struct rockchip_spi_driver_data *sdd;
- struct rockchip_spi_info *info = pdev->dev.platform_data;
- struct dw_spi *dws;
- int ret, irq;
- char clk_name[16];
-
- if (!info && pdev->dev.of_node) {
- info = rockchip_spi_parse_dt(&pdev->dev);
- if (IS_ERR(info))
- return PTR_ERR(info);
+ unsigned long flags;
+ struct rockchip_spi *rs = data;
+
+ /* Wait until the FIFO data completely. */
+ wait_for_idle(rs);
+
+ spin_lock_irqsave(&rs->lock, flags);
+
+ rs->state &= ~TXBUSY;
+ if (!(rs->state & RXBUSY)) {
+ spi_enable_chip(rs, 0);
+ spi_finalize_current_transfer(rs->master);
}
- if (!info) {
- dev_err(&pdev->dev, "platform_data missing!\n");
- return -ENODEV;
- }
+ spin_unlock_irqrestore(&rs->lock, flags);
+}
+
+static void rockchip_spi_prepare_dma(struct rockchip_spi *rs)
+{
+ unsigned long flags;
+ struct dma_slave_config rxconf, txconf;
+ struct dma_async_tx_descriptor *rxdesc, *txdesc;
+
+ spin_lock_irqsave(&rs->lock, flags);
+ rs->state &= ~RXBUSY;
+ rs->state &= ~TXBUSY;
+ spin_unlock_irqrestore(&rs->lock, flags);
+
+ rxdesc = NULL;
+ if (rs->rx) {
+ rxconf.direction = rs->dma_rx.direction;
+ rxconf.src_addr = rs->dma_rx.addr;
+ rxconf.src_addr_width = rs->n_bytes;
+ rxconf.src_maxburst = rs->n_bytes;
+ dmaengine_slave_config(rs->dma_rx.ch, &rxconf);
+
+ rxdesc = dmaengine_prep_slave_sg(
+ rs->dma_rx.ch,
+ rs->rx_sg.sgl, rs->rx_sg.nents,
+ rs->dma_rx.direction, DMA_PREP_INTERRUPT);
+
+ rxdesc->callback = rockchip_spi_dma_rxcb;
+ rxdesc->callback_param = rs;
+ }
- sdd = kzalloc(sizeof(struct rockchip_spi_driver_data), GFP_KERNEL);
- if (!sdd) {
- ret = -ENOMEM;
- goto err_kfree;
+ txdesc = NULL;
+ if (rs->tx) {
+ txconf.direction = rs->dma_tx.direction;
+ txconf.dst_addr = rs->dma_tx.addr;
+ txconf.dst_addr_width = rs->n_bytes;
+ txconf.dst_maxburst = rs->n_bytes;
+ dmaengine_slave_config(rs->dma_tx.ch, &txconf);
+
+ txdesc = dmaengine_prep_slave_sg(
+ rs->dma_tx.ch,
+ rs->tx_sg.sgl, rs->tx_sg.nents,
+ rs->dma_tx.direction, DMA_PREP_INTERRUPT);
+
+ txdesc->callback = rockchip_spi_dma_txcb;
+ txdesc->callback_param = rs;
}
-
- sdd->pdev = pdev;
- sdd->info = info;
- dws = &sdd->dws;
+ /* rx must be started before tx due to spi instinct */
+ if (rxdesc) {
+ spin_lock_irqsave(&rs->lock, flags);
+ rs->state |= RXBUSY;
+ spin_unlock_irqrestore(&rs->lock, flags);
+ dmaengine_submit(rxdesc);
+ dma_async_issue_pending(rs->dma_rx.ch);
+ }
- atomic_set(&dws->debug_flag, 0);//debug flag
+ if (txdesc) {
+ spin_lock_irqsave(&rs->lock, flags);
+ rs->state |= TXBUSY;
+ spin_unlock_irqrestore(&rs->lock, flags);
+ dmaengine_submit(txdesc);
+ dma_async_issue_pending(rs->dma_tx.ch);
+ }
+}
- /* Get basic io resource and map it */
- irq = platform_get_irq(pdev, 0);
- if (irq < 0) {
- dev_warn(&pdev->dev, "Failed to get IRQ: %d\n", irq);
- return irq;
+static void rockchip_spi_config(struct rockchip_spi *rs)
+{
+ u32 div = 0;
+ u32 dmacr = 0;
+ int rsd = 0;
+
+ u32 cr0 = (CR0_BHT_8BIT << CR0_BHT_OFFSET)
+ | (CR0_SSD_ONE << CR0_SSD_OFFSET);
+
+ cr0 |= (rs->n_bytes << CR0_DFS_OFFSET);
+ cr0 |= ((rs->mode & 0x3) << CR0_SCPH_OFFSET);
+ cr0 |= (rs->tmode << CR0_XFM_OFFSET);
+ cr0 |= (rs->type << CR0_FRF_OFFSET);
+
+ if (rs->use_dma) {
+ if (rs->tx)
+ dmacr |= TF_DMA_EN;
+ if (rs->rx)
+ dmacr |= RF_DMA_EN;
}
-
- mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- if (mem_res == NULL) {
- dev_err(&pdev->dev, "Unable to get SPI MEM resource\n");
- ret = -ENXIO;
- goto err_unmap;
+
+ if (WARN_ON(rs->speed > MAX_SCLK_OUT))
+ rs->speed = MAX_SCLK_OUT;
+
+ /* the minimum divsor is 2 */
+ if (rs->max_freq < 2 * rs->speed) {
+ clk_set_rate(rs->spiclk, 2 * rs->speed);
+ rs->max_freq = clk_get_rate(rs->spiclk);
}
-
- dws->regs = ioremap(mem_res->start, (mem_res->end - mem_res->start) + 1);
- if (!dws->regs){
- ret = -EBUSY;
- goto err_unmap;
+
+ /* div doesn't support odd number */
+ div = DIV_ROUND_UP(rs->max_freq, rs->speed);
+ div = (div + 1) & 0xfffe;
+
+ /* Rx sample delay is expressed in parent clock cycles (max 3) */
+ rsd = DIV_ROUND_CLOSEST(rs->rsd_nsecs * (rs->max_freq >> 8),
+ 1000000000 >> 8);
+ if (!rsd && rs->rsd_nsecs) {
+ pr_warn_once("rockchip-spi: %u Hz are too slow to express %u ns delay\n",
+ rs->max_freq, rs->rsd_nsecs);
+ } else if (rsd > 3) {
+ rsd = 3;
+ pr_warn_once("rockchip-spi: %u Hz are too fast to express %u ns delay, clamping at %u ns\n",
+ rs->max_freq, rs->rsd_nsecs,
+ rsd * 1000000000U / rs->max_freq);
}
+ cr0 |= rsd << CR0_RSD_OFFSET;
- dws->paddr = mem_res->start;
- dws->iolen = (mem_res->end - mem_res->start) + 1;
-
- printk(KERN_INFO "dws->regs: %p\n", dws->regs);
+ writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0);
- //get bus num
- if (pdev->dev.of_node) {
- ret = of_alias_get_id(pdev->dev.of_node, "spi");
- if (ret < 0) {
- dev_err(&pdev->dev, "failed to get alias id, errno %d\n",
- ret);
- goto err_release_mem;
+ writel_relaxed(rs->len - 1, rs->regs + ROCKCHIP_SPI_CTRLR1);
+ writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_TXFTLR);
+ writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_RXFTLR);
+
+ writel_relaxed(0, rs->regs + ROCKCHIP_SPI_DMATDLR);
+ writel_relaxed(0, rs->regs + ROCKCHIP_SPI_DMARDLR);
+ writel_relaxed(dmacr, rs->regs + ROCKCHIP_SPI_DMACR);
+
+ spi_set_clk(rs, div);
+
+ dev_dbg(rs->dev, "cr0 0x%x, div %d\n", cr0, div);
+}
+
+static int rockchip_spi_transfer_one(
+ struct spi_master *master,
+ struct spi_device *spi,
+ struct spi_transfer *xfer)
+{
+ int ret = 1;
+ struct rockchip_spi *rs = spi_master_get_devdata(master);
+
+ WARN_ON(readl_relaxed(rs->regs + ROCKCHIP_SPI_SSIENR) &&
+ (readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY));
+
+ if (!xfer->tx_buf && !xfer->rx_buf) {
+ dev_err(rs->dev, "No buffer for transfer\n");
+ return -EINVAL;
+ }
+
+ rs->speed = xfer->speed_hz;
+ rs->bpw = xfer->bits_per_word;
+ rs->n_bytes = rs->bpw >> 3;
+
+ rs->tx = xfer->tx_buf;
+ rs->tx_end = rs->tx + xfer->len;
+ rs->rx = xfer->rx_buf;
+ rs->rx_end = rs->rx + xfer->len;
+ rs->len = xfer->len;
+
+ rs->tx_sg = xfer->tx_sg;
+ rs->rx_sg = xfer->rx_sg;
+
+ if (rs->tx && rs->rx)
+ rs->tmode = CR0_XFM_TR;
+ else if (rs->tx)
+ rs->tmode = CR0_XFM_TO;
+ else if (rs->rx)
+ rs->tmode = CR0_XFM_RO;
+
+ /* we need prepare dma before spi was enabled */
+ if (master->can_dma && master->can_dma(master, spi, xfer))
+ rs->use_dma = 1;
+ else
+ rs->use_dma = 0;
+
+ rockchip_spi_config(rs);
+
+ if (rs->use_dma) {
+ if (rs->tmode == CR0_XFM_RO) {
+ /* rx: dma must be prepared first */
+ rockchip_spi_prepare_dma(rs);
+ spi_enable_chip(rs, 1);
+ } else {
+ /* tx or tr: spi must be enabled first */
+ spi_enable_chip(rs, 1);
+ rockchip_spi_prepare_dma(rs);
}
- info->bus_num = ret;
} else {
- info->bus_num = pdev->id;
+ spi_enable_chip(rs, 1);
+ ret = rockchip_spi_pio_transfer(rs);
+ }
+
+ return ret;
+}
+
+static bool rockchip_spi_can_dma(struct spi_master *master,
+ struct spi_device *spi,
+ struct spi_transfer *xfer)
+{
+ struct rockchip_spi *rs = spi_master_get_devdata(master);
+
+ return (xfer->len > rs->fifo_len);
+}
+
+static int rockchip_spi_probe(struct platform_device *pdev)
+{
+ int ret = 0;
+ struct rockchip_spi *rs;
+ struct spi_master *master;
+ struct resource *mem;
+ u32 rsd_nsecs;
+
+ master = spi_alloc_master(&pdev->dev, sizeof(struct rockchip_spi));
+ if (!master)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, master);
+
+ rs = spi_master_get_devdata(master);
+
+ /* Get basic io resource and map it */
+ mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ rs->regs = devm_ioremap_resource(&pdev->dev, mem);
+ if (IS_ERR(rs->regs)) {
+ ret = PTR_ERR(rs->regs);
+ goto err_ioremap_resource;
}
- /* Setup clocks */
- sdd->clk_spi = devm_clk_get(&pdev->dev, "spi");
- if (IS_ERR(sdd->clk_spi)) {
- dev_err(&pdev->dev, "Unable to acquire clock 'spi'\n");
- ret = PTR_ERR(sdd->clk_spi);
- goto err_clk;
+ rs->apb_pclk = devm_clk_get(&pdev->dev, "apb_pclk");
+ if (IS_ERR(rs->apb_pclk)) {
+ dev_err(&pdev->dev, "Failed to get apb_pclk\n");
+ ret = PTR_ERR(rs->apb_pclk);
+ goto err_ioremap_resource;
}
- if (clk_prepare_enable(sdd->clk_spi)) {
- dev_err(&pdev->dev, "Couldn't enable clock 'spi'\n");
- ret = -EBUSY;
- goto err_clk;
+ rs->spiclk = devm_clk_get(&pdev->dev, "spiclk");
+ if (IS_ERR(rs->spiclk)) {
+ dev_err(&pdev->dev, "Failed to get spi_pclk\n");
+ ret = PTR_ERR(rs->spiclk);
+ goto err_ioremap_resource;
}
-
- sprintf(clk_name, "pclk_spi%d", info->src_clk_nr);
- sdd->pclk_spi = devm_clk_get(&pdev->dev, clk_name);
- if (IS_ERR(sdd->pclk_spi)) {
- dev_err(&pdev->dev,
- "Unable to acquire clock '%s'\n", clk_name);
- ret = PTR_ERR(sdd->pclk_spi);
- goto err_pclk;
+
+ ret = clk_prepare_enable(rs->apb_pclk);
+ if (ret) {
+ dev_err(&pdev->dev, "Failed to enable apb_pclk\n");
+ goto err_ioremap_resource;
}
- if (clk_prepare_enable(sdd->pclk_spi)) {
- dev_err(&pdev->dev, "Couldn't enable clock '%s'\n", clk_name);
- ret = -EBUSY;
- goto err_pclk;
+ ret = clk_prepare_enable(rs->spiclk);
+ if (ret) {
+ dev_err(&pdev->dev, "Failed to enable spi_clk\n");
+ goto err_spiclk_enable;
}
- clk_set_rate(sdd->clk_spi, info->spi_freq);
-
- dws->max_freq = clk_get_rate(sdd->clk_spi);
- dws->parent_dev = &pdev->dev;
- dws->bus_num = info->bus_num;
- dws->num_cs = info->num_cs;
- dws->irq = irq;
- dws->clk_spi = sdd->clk_spi;
- dws->pclk_spi = sdd->pclk_spi;
+ spi_enable_chip(rs, 0);
- /*
- * handling for rockchip paltforms, like dma setup,
- * clock rate, FIFO depth.
- */
-
-#ifdef CONFIG_SPI_ROCKCHIP_DMA
- ret = dw_spi_dma_init(dws);
- if (ret)
- printk("%s:fail to init dma\n",__func__);
-#endif
+ rs->type = SSI_MOTO_SPI;
+ rs->master = master;
+ rs->dev = &pdev->dev;
+ rs->max_freq = clk_get_rate(rs->spiclk);
- ret = dw_spi_add_host(dws);
- if (ret)
- goto err_release_mem;
+ if (!of_property_read_u32(pdev->dev.of_node, "rx-sample-delay-ns",
+ &rsd_nsecs))
+ rs->rsd_nsecs = rsd_nsecs;
+
+ rs->fifo_len = get_fifo_len(rs);
+ if (!rs->fifo_len) {
+ dev_err(&pdev->dev, "Failed to get fifo length\n");
+ ret = -EINVAL;
+ goto err_get_fifo_len;
+ }
+
+ spin_lock_init(&rs->lock);
+
+ pm_runtime_set_active(&pdev->dev);
+ pm_runtime_enable(&pdev->dev);
+
+ master->auto_runtime_pm = true;
+ master->bus_num = pdev->id;
+ master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP;
+ master->num_chipselect = 2;
+ master->dev.of_node = pdev->dev.of_node;
+ master->bits_per_word_mask = SPI_BPW_MASK(16) | SPI_BPW_MASK(8);
+
+ master->set_cs = rockchip_spi_set_cs;
+ master->prepare_message = rockchip_spi_prepare_message;
+ master->unprepare_message = rockchip_spi_unprepare_message;
+ master->transfer_one = rockchip_spi_transfer_one;
+ master->handle_err = rockchip_spi_handle_err;
+
+ rs->dma_tx.ch = dma_request_slave_channel(rs->dev, "tx");
+ if (!rs->dma_tx.ch)
+ dev_warn(rs->dev, "Failed to request TX DMA channel\n");
+
+ rs->dma_rx.ch = dma_request_slave_channel(rs->dev, "rx");
+ if (!rs->dma_rx.ch) {
+ if (rs->dma_tx.ch) {
+ dma_release_channel(rs->dma_tx.ch);
+ rs->dma_tx.ch = NULL;
+ }
+ dev_warn(rs->dev, "Failed to request RX DMA channel\n");
+ }
- platform_set_drvdata(pdev, sdd);
+ if (rs->dma_tx.ch && rs->dma_rx.ch) {
+ rs->dma_tx.addr = (dma_addr_t)(mem->start + ROCKCHIP_SPI_TXDR);
+ rs->dma_rx.addr = (dma_addr_t)(mem->start + ROCKCHIP_SPI_RXDR);
+ rs->dma_tx.direction = DMA_MEM_TO_DEV;
+ rs->dma_rx.direction = DMA_DEV_TO_MEM;
+
+ master->can_dma = rockchip_spi_can_dma;
+ master->dma_tx = rs->dma_tx.ch;
+ master->dma_rx = rs->dma_rx.ch;
+ }
+
+ ret = devm_spi_register_master(&pdev->dev, master);
+ if (ret) {
+ dev_err(&pdev->dev, "Failed to register master\n");
+ goto err_register_master;
+ }
- printk("%s:num_cs=%d,bus_num=%d,irq=%d,freq=%d ok\n",__func__, info->num_cs, info->bus_num, irq, dws->max_freq);
-
return 0;
-err_release_mem:
- release_mem_region(mem_res->start, (mem_res->end - mem_res->start) + 1);
-err_pclk:
- clk_disable_unprepare(sdd->pclk_spi);
-err_clk:
- clk_disable_unprepare(sdd->clk_spi);
-err_unmap:
- iounmap(dws->regs);
-err_kfree:
- kfree(sdd);
+
+err_register_master:
+ pm_runtime_disable(&pdev->dev);
+ if (rs->dma_tx.ch)
+ dma_release_channel(rs->dma_tx.ch);
+ if (rs->dma_rx.ch)
+ dma_release_channel(rs->dma_rx.ch);
+err_get_fifo_len:
+ clk_disable_unprepare(rs->spiclk);
+err_spiclk_enable:
+ clk_disable_unprepare(rs->apb_pclk);
+err_ioremap_resource:
+ spi_master_put(master);
+
return ret;
}
static int rockchip_spi_remove(struct platform_device *pdev)
{
- struct rockchip_spi_driver_data *sdd = platform_get_drvdata(pdev);
-
- platform_set_drvdata(pdev, NULL);
- dw_spi_remove_host(&sdd->dws);
- iounmap(sdd->dws.regs);
- kfree(sdd);
+ struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
+ struct rockchip_spi *rs = spi_master_get_devdata(master);
+
+ pm_runtime_disable(&pdev->dev);
+
+ clk_disable_unprepare(rs->spiclk);
+ clk_disable_unprepare(rs->apb_pclk);
+
+ if (rs->dma_tx.ch)
+ dma_release_channel(rs->dma_tx.ch);
+ if (rs->dma_rx.ch)
+ dma_release_channel(rs->dma_rx.ch);
+
+ spi_master_put(master);
return 0;
}
#ifdef CONFIG_PM_SLEEP
static int rockchip_spi_suspend(struct device *dev)
{
- struct rockchip_spi_driver_data *sdd = dev_get_drvdata(dev);
int ret = 0;
-
- ret = dw_spi_suspend_host(&sdd->dws);
-
+ struct spi_master *master = dev_get_drvdata(dev);
+ struct rockchip_spi *rs = spi_master_get_devdata(master);
+
+ ret = spi_master_suspend(rs->master);
+ if (ret)
+ return ret;
+
+ if (!pm_runtime_suspended(dev)) {
+ clk_disable_unprepare(rs->spiclk);
+ clk_disable_unprepare(rs->apb_pclk);
+ }
+
return ret;
}
static int rockchip_spi_resume(struct device *dev)
{
- struct rockchip_spi_driver_data *sdd = dev_get_drvdata(dev);
int ret = 0;
-
- ret = dw_spi_resume_host(&sdd->dws);
+ struct spi_master *master = dev_get_drvdata(dev);
+ struct rockchip_spi *rs = spi_master_get_devdata(master);
+
+ if (!pm_runtime_suspended(dev)) {
+ ret = clk_prepare_enable(rs->apb_pclk);
+ if (ret < 0)
+ return ret;
+
+ ret = clk_prepare_enable(rs->spiclk);
+ if (ret < 0) {
+ clk_disable_unprepare(rs->apb_pclk);
+ return ret;
+ }
+ }
+
+ ret = spi_master_resume(rs->master);
+ if (ret < 0) {
+ clk_disable_unprepare(rs->spiclk);
+ clk_disable_unprepare(rs->apb_pclk);
+ }
return ret;
}
#endif /* CONFIG_PM_SLEEP */
-#ifdef CONFIG_PM_RUNTIME
+#ifdef CONFIG_PM
static int rockchip_spi_runtime_suspend(struct device *dev)
{
- struct rockchip_spi_driver_data *sdd = dev_get_drvdata(dev);
- struct dw_spi *dws = &sdd->dws;
-
- clk_disable_unprepare(sdd->clk_spi);
- clk_disable_unprepare(sdd->pclk_spi);
-
-
- DBG_SPI("%s\n",__func__);
-
+ struct spi_master *master = dev_get_drvdata(dev);
+ struct rockchip_spi *rs = spi_master_get_devdata(master);
+
+ clk_disable_unprepare(rs->spiclk);
+ clk_disable_unprepare(rs->apb_pclk);
+
return 0;
}
static int rockchip_spi_runtime_resume(struct device *dev)
{
- struct rockchip_spi_driver_data *sdd = dev_get_drvdata(dev);
- struct dw_spi *dws = &sdd->dws;
+ int ret;
+ struct spi_master *master = dev_get_drvdata(dev);
+ struct rockchip_spi *rs = spi_master_get_devdata(master);
- clk_prepare_enable(sdd->pclk_spi);
- clk_prepare_enable(sdd->clk_spi);
-
- DBG_SPI("%s\n",__func__);
- return 0;
+ ret = clk_prepare_enable(rs->apb_pclk);
+ if (ret)
+ return ret;
+
+ ret = clk_prepare_enable(rs->spiclk);
+ if (ret)
+ clk_disable_unprepare(rs->apb_pclk);
+
+ return ret;
}
-#endif /* CONFIG_PM_RUNTIME */
+#endif /* CONFIG_PM */
static const struct dev_pm_ops rockchip_spi_pm = {
SET_SYSTEM_SLEEP_PM_OPS(rockchip_spi_suspend, rockchip_spi_resume)
rockchip_spi_runtime_resume, NULL)
};
-#ifdef CONFIG_OF
static const struct of_device_id rockchip_spi_dt_match[] = {
- { .compatible = "rockchip,rockchip-spi",
- },
+ { .compatible = "rockchip,rk3066-spi", },
+ { .compatible = "rockchip,rk3188-spi", },
+ { .compatible = "rockchip,rk3288-spi", },
+ { .compatible = "rockchip,rk3399-spi", },
{ },
};
MODULE_DEVICE_TABLE(of, rockchip_spi_dt_match);
-#endif /* CONFIG_OF */
static struct platform_driver rockchip_spi_driver = {
.driver = {
- .name = "rockchip-spi",
- .owner = THIS_MODULE,
+ .name = DRIVER_NAME,
.pm = &rockchip_spi_pm,
.of_match_table = of_match_ptr(rockchip_spi_dt_match),
},
+ .probe = rockchip_spi_probe,
.remove = rockchip_spi_remove,
};
-MODULE_ALIAS("platform:rockchip-spi");
-
-static int __init rockchip_spi_init(void)
-{
- return platform_driver_probe(&rockchip_spi_driver, rockchip_spi_probe);
-}
-module_init(rockchip_spi_init);
-static void __exit rockchip_spi_exit(void)
-{
- platform_driver_unregister(&rockchip_spi_driver);
-}
-module_exit(rockchip_spi_exit);
+module_platform_driver(rockchip_spi_driver);
-MODULE_AUTHOR("Luo Wei <lw@rock-chips.com>");
+MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>");
MODULE_DESCRIPTION("ROCKCHIP SPI Controller Driver");
-MODULE_LICENSE("GPL");
+MODULE_LICENSE("GPL v2");
projects / firefly-linux-kernel-4.4.55.git / blobdiff