*
* Copyright (c) 2016 Rockchip, Inc.
*
- * Based on the xilinx PCIe driver
+ * Author: Shawn Lin <shawn.lin@rock-chips.com>
+ * Wenrui Li <wenrui.li@rock-chips.com>
*
* Bits taken from Synopsys Designware Host controller driver and
* ARM PCI Host generic driver.
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*/
+
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/gpio/consumer.h>
+#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
+#include <linux/irqchip/chained_irq.h>
#include <linux/irqdomain.h>
#include <linux/kernel.h>
#include <linux/mfd/syscon.h>
-#include <linux/module.h>
-#include <linux/msi.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/of_pci.h>
#include <linux/of_platform.h>
#include <linux/of_irq.h>
#include <linux/pci.h>
+#include <linux/pci_ids.h>
+#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/reset.h>
#include <linux/regmap.h>
-#define REF_CLK_100MHZ (100 * 1000 * 1000)
+/*
+ * The upper 16 bits of PCIE_CLIENT_CONFIG are a write mask for the lower 16
+ * bits. This allows atomic updates of the register without locking.
+ */
+#define HIWORD_UPDATE(mask, val) (((mask) << 16) | (val))
+#define HIWORD_UPDATE_BIT(val) HIWORD_UPDATE(val, val)
+
+#define ENCODE_LANES(x) ((((x) >> 1) & 3) << 4)
+
#define PCIE_CLIENT_BASE 0x0
-#define PCIE_RC_CONFIG_BASE 0xa00000
+#define PCIE_CLIENT_CONFIG (PCIE_CLIENT_BASE + 0x00)
+#define PCIE_CLIENT_CONF_ENABLE HIWORD_UPDATE_BIT(0x0001)
+#define PCIE_CLIENT_LINK_TRAIN_ENABLE HIWORD_UPDATE_BIT(0x0002)
+#define PCIE_CLIENT_ARI_ENABLE HIWORD_UPDATE_BIT(0x0008)
+#define PCIE_CLIENT_CONF_LANE_NUM(x) HIWORD_UPDATE(0x0030, ENCODE_LANES(x))
+#define PCIE_CLIENT_MODE_RC HIWORD_UPDATE_BIT(0x0040)
+#define PCIE_CLIENT_GEN_SEL_2 HIWORD_UPDATE_BIT(0x0080)
+#define PCIE_CLIENT_BASIC_STATUS1 (PCIE_CLIENT_BASE + 0x48)
+#define PCIE_CLIENT_LINK_STATUS_UP 0x00300000
+#define PCIE_CLIENT_LINK_STATUS_MASK 0x00300000
+#define PCIE_CLIENT_INT_MASK (PCIE_CLIENT_BASE + 0x4c)
+#define PCIE_CLIENT_INT_STATUS (PCIE_CLIENT_BASE + 0x50)
+#define PCIE_CLIENT_INTR_MASK GENMASK(8, 5)
+#define PCIE_CLIENT_INTR_SHIFT 5
+#define PCIE_CLIENT_INT_LEGACY_DONE BIT(15)
+#define PCIE_CLIENT_INT_MSG BIT(14)
+#define PCIE_CLIENT_INT_HOT_RST BIT(13)
+#define PCIE_CLIENT_INT_DPA BIT(12)
+#define PCIE_CLIENT_INT_FATAL_ERR BIT(11)
+#define PCIE_CLIENT_INT_NFATAL_ERR BIT(10)
+#define PCIE_CLIENT_INT_CORR_ERR BIT(9)
+#define PCIE_CLIENT_INT_INTD BIT(8)
+#define PCIE_CLIENT_INT_INTC BIT(7)
+#define PCIE_CLIENT_INT_INTB BIT(6)
+#define PCIE_CLIENT_INT_INTA BIT(5)
+#define PCIE_CLIENT_INT_LOCAL BIT(4)
+#define PCIE_CLIENT_INT_UDMA BIT(3)
+#define PCIE_CLIENT_INT_PHY BIT(2)
+#define PCIE_CLIENT_INT_HOT_PLUG BIT(1)
+#define PCIE_CLIENT_INT_PWR_STCG BIT(0)
+
+#define PCIE_CLIENT_INT_LEGACY \
+ (PCIE_CLIENT_INT_INTA | PCIE_CLIENT_INT_INTB | \
+ PCIE_CLIENT_INT_INTC | PCIE_CLIENT_INT_INTD)
+
+#define PCIE_CLIENT_INT_CLI \
+ (PCIE_CLIENT_INT_CORR_ERR | PCIE_CLIENT_INT_NFATAL_ERR | \
+ PCIE_CLIENT_INT_FATAL_ERR | PCIE_CLIENT_INT_DPA | \
+ PCIE_CLIENT_INT_HOT_RST | PCIE_CLIENT_INT_MSG | \
+ PCIE_CLIENT_INT_LEGACY_DONE | PCIE_CLIENT_INT_LEGACY | \
+ PCIE_CLIENT_INT_PHY)
+
#define PCIE_CORE_CTRL_MGMT_BASE 0x900000
+#define PCIE_CORE_CTRL (PCIE_CORE_CTRL_MGMT_BASE + 0x000)
+#define PCIE_CORE_PL_CONF_SPEED_5G 0x00000008
+#define PCIE_CORE_PL_CONF_SPEED_MASK 0x00000018
+#define PCIE_CORE_PL_CONF_LANE_MASK 0x00000006
+#define PCIE_CORE_PL_CONF_LANE_SHIFT 1
+#define PCIE_CORE_CTRL_PLC1 (PCIE_CORE_CTRL_MGMT_BASE + 0x004)
+#define PCIE_CORE_CTRL_PLC1_FTS_MASK GENMASK(23, 8)
+#define PCIE_CORE_CTRL_PLC1_FTS_SHIFT 8
+#define PCIE_CORE_CTRL_PLC1_FTS_CNT 0xffff
+#define PCIE_CORE_TXCREDIT_CFG1 (PCIE_CORE_CTRL_MGMT_BASE + 0x020)
+#define PCIE_CORE_TXCREDIT_CFG1_MUI_MASK 0xFFFF0000
+#define PCIE_CORE_TXCREDIT_CFG1_MUI_SHIFT 16
+#define PCIE_CORE_TXCREDIT_CFG1_MUI_ENCODE(x) \
+ (((x) >> 3) << PCIE_CORE_TXCREDIT_CFG1_MUI_SHIFT)
+#define PCIE_CORE_INT_STATUS (PCIE_CORE_CTRL_MGMT_BASE + 0x20c)
+#define PCIE_CORE_INT_PRFPE BIT(0)
+#define PCIE_CORE_INT_CRFPE BIT(1)
+#define PCIE_CORE_INT_RRPE BIT(2)
+#define PCIE_CORE_INT_PRFO BIT(3)
+#define PCIE_CORE_INT_CRFO BIT(4)
+#define PCIE_CORE_INT_RT BIT(5)
+#define PCIE_CORE_INT_RTR BIT(6)
+#define PCIE_CORE_INT_PE BIT(7)
+#define PCIE_CORE_INT_MTR BIT(8)
+#define PCIE_CORE_INT_UCR BIT(9)
+#define PCIE_CORE_INT_FCE BIT(10)
+#define PCIE_CORE_INT_CT BIT(11)
+#define PCIE_CORE_INT_UTC BIT(18)
+#define PCIE_CORE_INT_MMVC BIT(19)
+#define PCIE_CORE_INT_MASK (PCIE_CORE_CTRL_MGMT_BASE + 0x210)
+#define PCIE_RC_BAR_CONF (PCIE_CORE_CTRL_MGMT_BASE + 0x300)
+
+#define PCIE_CORE_INT \
+ (PCIE_CORE_INT_PRFPE | PCIE_CORE_INT_CRFPE | \
+ PCIE_CORE_INT_RRPE | PCIE_CORE_INT_CRFO | \
+ PCIE_CORE_INT_RT | PCIE_CORE_INT_RTR | \
+ PCIE_CORE_INT_PE | PCIE_CORE_INT_MTR | \
+ PCIE_CORE_INT_UCR | PCIE_CORE_INT_FCE | \
+ PCIE_CORE_INT_CT | PCIE_CORE_INT_UTC | \
+ PCIE_CORE_INT_MMVC)
+
+#define PCIE_RC_CONFIG_BASE 0xa00000
+#define PCIE_RC_CONFIG_VENDOR (PCIE_RC_CONFIG_BASE + 0x00)
+#define PCIE_RC_CONFIG_RID_CCR (PCIE_RC_CONFIG_BASE + 0x08)
+#define PCIE_RC_CONFIG_SCC_SHIFT 16
+#define PCIE_RC_CONFIG_DCR (PCIE_RC_CONFIG_BASE + 0xc4)
+#define PCIE_RC_CONFIG_DCR_CSPL_SHIFT 18
+#define PCIE_RC_CONFIG_DCR_CSPL_LIMIT 0xff
+#define PCIE_RC_CONFIG_DCR_CPLS_SHIFT 26
+#define PCIE_RC_CONFIG_LCS (PCIE_RC_CONFIG_BASE + 0xd0)
+#define PCIE_RC_CONFIG_LCS_RETRAIN_LINK BIT(5)
+#define PCIE_RC_CONFIG_LCS_CCC BIT(6)
+#define PCIE_RC_CONFIG_LCS_LBMIE BIT(10)
+#define PCIE_RC_CONFIG_LCS_LABIE BIT(11)
+#define PCIE_RC_CONFIG_LCS_LBMS BIT(30)
+#define PCIE_RC_CONFIG_LCS_LAMS BIT(31)
+#define PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2 (PCIE_RC_CONFIG_BASE + 0x90c)
+
#define PCIE_CORE_AXI_CONF_BASE 0xc00000
-#define PCIE_CORE_AXI_INBOUND_BASE 0xc00800
+#define PCIE_CORE_OB_REGION_ADDR0 (PCIE_CORE_AXI_CONF_BASE + 0x0)
+#define PCIE_CORE_OB_REGION_ADDR0_NUM_BITS 0x3f
+#define PCIE_CORE_OB_REGION_ADDR0_LO_ADDR 0xffffff00
+#define PCIE_CORE_OB_REGION_ADDR1 (PCIE_CORE_AXI_CONF_BASE + 0x4)
+#define PCIE_CORE_OB_REGION_DESC0 (PCIE_CORE_AXI_CONF_BASE + 0x8)
+#define PCIE_CORE_OB_REGION_DESC1 (PCIE_CORE_AXI_CONF_BASE + 0xc)
-#define PCIE_CLIENT_BASIC_STATUS0 0x44
-#define PCIE_CLIENT_BASIC_STATUS1 0x48
-#define PCIE_CLIENT_INT_MASK 0x4c
-#define PCIE_CLIENT_INT_STATUS 0x50
-#define PCIE_CORE_INT_MASK 0x900210
-#define PCIE_CORE_INT_STATUS 0x90020c
-
-/** Size of one AXI Region (not Region 0) */
-#define AXI_REGION_SIZE (0x1 << 20)
-/** Overall size of AXI area */
-#define AXI_OVERALL_SIZE (64 * (0x1 << 20))
-/** Size of Region 0, equal to sum of sizes of other regions */
-#define AXI_REGION_0_SIZE (32 * (0x1 << 20))
-#define OB_REG_SIZE_SHIFT 5
-#define IB_ROOT_PORT_REG_SIZE_SHIFT 3
-
-#define AXI_WRAPPER_IO_WRITE 0x6
-#define AXI_WRAPPER_MEM_WRITE 0x2
-#define MAX_AXI_IB_ROOTPORT_REGION_NUM 3
-#define MIN_AXI_ADDR_BITS_PASSED 8
-
-#define ROCKCHIP_PCIE_RPIFR1_INTR_MASK GENMASK(8, 5)
-#define ROCKCHIP_PCIE_RPIFR1_INTR_SHIFT 5
-#define CLIENT_INTERRUPTS \
- (LOC_INT | INTA | INTB | INTC | INTD |\
- CORR_ERR | NFATAL_ERR | FATAL_ERR | DPA_INT | \
- HOT_RESET | MSG_DONE | LEGACY_DONE)
-#define CORE_INTERRUPTS \
- (PRFPE | CRFPE | RRPE | CRFO | RT | RTR | \
- PE | MTR | UCR | FCE | CT | UTC | MMVC)
-#define PWR_STCG BIT(0)
-#define HOT_PLUG BIT(1)
-#define PHY_INT BIT(2)
-#define UDMA_INT BIT(3)
-#define LOC_INT BIT(4)
-#define INTA BIT(5)
-#define INTB BIT(6)
-#define INTC BIT(7)
-#define INTD BIT(8)
-#define CORR_ERR BIT(9)
-#define NFATAL_ERR BIT(10)
-#define FATAL_ERR BIT(11)
-#define DPA_INT BIT(12)
-#define HOT_RESET BIT(13)
-#define MSG_DONE BIT(14)
-#define LEGACY_DONE BIT(15)
-#define PRFPE BIT(0)
-#define CRFPE BIT(1)
-#define RRPE BIT(2)
-#define PRFO BIT(3)
-#define CRFO BIT(4)
-#define RT BIT(5)
-#define RTR BIT(6)
-#define PE BIT(7)
-#define MTR BIT(8)
-#define UCR BIT(9)
-#define FCE BIT(10)
-#define CT BIT(11)
-#define UTC BIT(18)
-#define MMVC BIT(19)
-
-#define PCIE_ECAM_BUS(x) (((x) & 0xFF) << 20)
-#define PCIE_ECAM_DEV(x) (((x) & 0x1F) << 15)
-#define PCIE_ECAM_FUNC(x) (((x) & 0x7) << 12)
-#define PCIE_ECAM_REG(x) (((x) & 0xFFF) << 0)
+#define PCIE_CORE_AXI_INBOUND_BASE 0xc00800
+#define PCIE_RP_IB_ADDR0 (PCIE_CORE_AXI_INBOUND_BASE + 0x0)
+#define PCIE_CORE_IB_REGION_ADDR0_NUM_BITS 0x3f
+#define PCIE_CORE_IB_REGION_ADDR0_LO_ADDR 0xffffff00
+#define PCIE_RP_IB_ADDR1 (PCIE_CORE_AXI_INBOUND_BASE + 0x4)
+
+/* Size of one AXI Region (not Region 0) */
+#define AXI_REGION_SIZE BIT(20)
+/* Size of Region 0, equal to sum of sizes of other regions */
+#define AXI_REGION_0_SIZE (32 * (0x1 << 20))
+#define OB_REG_SIZE_SHIFT 5
+#define IB_ROOT_PORT_REG_SIZE_SHIFT 3
+#define AXI_WRAPPER_IO_WRITE 0x6
+#define AXI_WRAPPER_MEM_WRITE 0x2
+
+#define MAX_AXI_IB_ROOTPORT_REGION_NUM 3
+#define MIN_AXI_ADDR_BITS_PASSED 8
+#define ROCKCHIP_VENDOR_ID 0x1d87
+#define PCIE_ECAM_BUS(x) (((x) & 0xff) << 20)
+#define PCIE_ECAM_DEV(x) (((x) & 0x1f) << 15)
+#define PCIE_ECAM_FUNC(x) (((x) & 0x7) << 12)
+#define PCIE_ECAM_REG(x) (((x) & 0xfff) << 0)
#define PCIE_ECAM_ADDR(bus, dev, func, reg) \
(PCIE_ECAM_BUS(bus) | PCIE_ECAM_DEV(dev) | \
PCIE_ECAM_FUNC(func) | PCIE_ECAM_REG(reg))
-#define RC_REGION_0_ADDR_TRANS_H 0x00000000
-#define RC_REGION_0_ADDR_TRANS_L 0x00000000
-#define RC_REGION_0_PASS_BITS (25 - 1)
-#define RC_REGION_1_ADDR_TRANS_H 0x00000000
-#define RC_REGION_1_ADDR_TRANS_L 0x00400000
-#define RC_REGION_1_PASS_BITS (20 - 1)
-#define MAX_AXI_WRAPPER_REGION_NUM 33
-#define PCIE_CLIENT_CONF_ENABLE BIT(0)
-#define PCIE_CLIENT_CONF_LANE_NUM(x) ((x / 2) << 4)
-#define PCIE_CLIENT_MODE_RC BIT(6)
-#define PCIE_CLIENT_GEN_SEL_2 BIT(7)
-#define PCIE_CLIENT_GEN_SEL_1 0x0
-
-struct rockchip_pcie_port {
- void __iomem *reg_base;
- void __iomem *apb_base;
- struct regmap *grf;
- unsigned int pcie_conf;
- unsigned int pcie_status;
- unsigned int pcie_laneoff;
- struct reset_control *phy_rst;
- struct reset_control *core_rst;
- struct reset_control *mgmt_rst;
- struct reset_control *mgmt_sticky_rst;
- struct reset_control *pipe_rst;
- struct clk *aclk_pcie;
- struct clk *aclk_perf_pcie;
- struct clk *hclk_pcie;
- struct clk *clk_pciephy_ref;
- struct gpio_desc *ep_gpio;
- u32 lanes;
- resource_size_t io_base;
- struct resource *cfg;
- struct resource *io;
- struct resource *mem;
- struct resource *busn;
- phys_addr_t io_bus_addr;
- u32 io_size;
- phys_addr_t mem_bus_addr;
- u32 mem_size;
+#define RC_REGION_0_ADDR_TRANS_H 0x00000000
+#define RC_REGION_0_ADDR_TRANS_L 0x00000000
+#define RC_REGION_0_PASS_BITS (25 - 1)
+#define MAX_AXI_WRAPPER_REGION_NUM 33
+
+struct rockchip_pcie {
+ void __iomem *reg_base; /* DT axi-base */
+ void __iomem *apb_base; /* DT apb-base */
+ struct phy *phy;
+ struct reset_control *core_rst;
+ struct reset_control *mgmt_rst;
+ struct reset_control *mgmt_sticky_rst;
+ struct reset_control *pipe_rst;
+ struct clk *aclk_pcie;
+ struct clk *aclk_perf_pcie;
+ struct clk *hclk_pcie;
+ struct clk *clk_pcie_pm;
+ struct regulator *vpcie3v3; /* 3.3V power supply */
+ struct regulator *vpcie1v8; /* 1.8V power supply */
+ struct regulator *vpcie0v9; /* 0.9V power supply */
+ struct gpio_desc *ep_gpio;
+ u32 lanes;
u8 root_bus_nr;
- int irq;
- struct msi_controller *msi;
-
- struct device *dev;
- struct irq_domain *irq_domain;
+ struct device *dev;
+ struct irq_domain *irq_domain;
};
-static inline u32 pcie_read(struct rockchip_pcie_port *port, u32 reg)
+static u32 rockchip_pcie_read(struct rockchip_pcie *rockchip, u32 reg)
+{
+ return readl(rockchip->apb_base + reg);
+}
+
+static void rockchip_pcie_write(struct rockchip_pcie *rockchip, u32 val,
+ u32 reg)
{
- return readl(port->apb_base + reg);
+ writel(val, rockchip->apb_base + reg);
}
-static inline void pcie_write(struct rockchip_pcie_port *port,
- u32 val, u32 reg)
+static void rockchip_pcie_enable_bw_int(struct rockchip_pcie *rockchip)
{
- writel(val, port->apb_base + reg);
+ u32 status;
+
+ status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);
+ status |= (PCIE_RC_CONFIG_LCS_LBMIE | PCIE_RC_CONFIG_LCS_LABIE);
+ rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
}
-static inline void pcie_pb_wr_cfg(struct rockchip_pcie_port *port,
- u32 addr, u32 data)
+static void rockchip_pcie_clr_bw_int(struct rockchip_pcie *rockchip)
{
- regmap_write(port->grf, port->pcie_conf,
- (0x3ff << 17) | (data << 7) | (addr << 1));
- udelay(1);
- regmap_write(port->grf, port->pcie_conf,
- (0x1 << 16) | (0x1 << 0));
- udelay(1);
- regmap_write(port->grf, port->pcie_conf,
- (0x1 << 16) | (0x0 << 0));
+ u32 status;
+
+ status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);
+ status |= (PCIE_RC_CONFIG_LCS_LBMS | PCIE_RC_CONFIG_LCS_LAMS);
+ rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
}
-static inline u32 pcie_pb_rd_cfg(struct rockchip_pcie_port *port,
- u32 addr)
+static void rockchip_pcie_update_txcredit_mui(struct rockchip_pcie *rockchip)
{
u32 val;
- regmap_write(port->grf, port->pcie_conf,
- (0x3ff << 17) | (addr << 1));
- regmap_read(port->grf, port->pcie_status, &val);
- return val;
+ /* Update Tx credit maximum update interval */
+ val = rockchip_pcie_read(rockchip, PCIE_CORE_TXCREDIT_CFG1);
+ val &= ~PCIE_CORE_TXCREDIT_CFG1_MUI_MASK;
+ val |= PCIE_CORE_TXCREDIT_CFG1_MUI_ENCODE(24000); /* ns */
+ rockchip_pcie_write(rockchip, val, PCIE_CORE_TXCREDIT_CFG1);
}
-static int rockchip_pcie_valid_config(struct rockchip_pcie_port *pp,
+static int rockchip_pcie_valid_device(struct rockchip_pcie *rockchip,
struct pci_bus *bus, int dev)
{
/* access only one slot on each root port */
- if (bus->number == pp->root_bus_nr && dev > 0)
+ if (bus->number == rockchip->root_bus_nr && dev > 0)
return 0;
/*
* do not read more than one device on the bus directly attached
- * to RC's (Virtual Bridge's) DS side.
+ * to RC's downstream side.
*/
- if (bus->primary == pp->root_bus_nr && dev > 0)
+ if (bus->primary == rockchip->root_bus_nr && dev > 0)
return 0;
return 1;
}
-static int rockchip_pcie_rd_own_conf(struct rockchip_pcie_port *pp,
- int where, int size,
- u32 *val)
+static int rockchip_pcie_rd_own_conf(struct rockchip_pcie *rockchip,
+ int where, int size, u32 *val)
{
- void __iomem *addr = pp->apb_base + PCIE_RC_CONFIG_BASE + where;
+ void __iomem *addr = rockchip->apb_base + PCIE_RC_CONFIG_BASE + where;
- if ((uintptr_t)addr & (size - 1)) {
+ if (!IS_ALIGNED((uintptr_t)addr, size)) {
*val = 0;
return PCIBIOS_BAD_REGISTER_NUMBER;
}
return PCIBIOS_SUCCESSFUL;
}
-static int rockchip_pcie_wr_own_conf(struct rockchip_pcie_port *pp,
+static int rockchip_pcie_wr_own_conf(struct rockchip_pcie *rockchip,
int where, int size, u32 val)
{
- u32 tmp;
- int offset;
+ u32 mask, tmp, offset;
- offset = (where & (~0x3));
- tmp = readl(pp->apb_base + PCIE_RC_CONFIG_BASE + offset);
- if (size == 4) {
- writel(val, pp->apb_base + PCIE_RC_CONFIG_BASE + where);
- } else if (size == 2) {
- if (where & 0x2)
- tmp = ((tmp & 0xffff) | (val << 16));
- else
- tmp = ((tmp & 0xffff0000) | val);
+ offset = where & ~0x3;
- writel(tmp, pp->apb_base + PCIE_RC_CONFIG_BASE + offset);
- } else if (size == 1) {
- if ((where & 0x3) == 0)
- tmp = ((tmp & (~0xff)) | val);
- else if ((where & 0x3) == 1)
- tmp = ((tmp & (~0xff00)) | (val << 8));
- else if ((where & 0x3) == 2)
- tmp = ((tmp & (~0xff0000)) | (val << 16));
- else if ((where & 0x3) == 3)
- tmp = ((tmp & (~0xff000000)) | (val << 24));
-
- writel(tmp, pp->apb_base + PCIE_RC_CONFIG_BASE + offset);
- } else {
- return PCIBIOS_BAD_REGISTER_NUMBER;
+ if (size == 4) {
+ writel(val, rockchip->apb_base + PCIE_RC_CONFIG_BASE + offset);
+ return PCIBIOS_SUCCESSFUL;
}
+
+ mask = ~(((1 << (size * 8)) - 1) << ((where & 0x3) * 8));
+
+ /*
+ * N.B. This read/modify/write isn't safe in general because it can
+ * corrupt RW1C bits in adjacent registers. But the hardware
+ * doesn't support smaller writes.
+ */
+ tmp = readl(rockchip->apb_base + PCIE_RC_CONFIG_BASE + offset) & mask;
+ tmp |= val << ((where & 0x3) * 8);
+ writel(tmp, rockchip->apb_base + PCIE_RC_CONFIG_BASE + offset);
+
return PCIBIOS_SUCCESSFUL;
}
-static int rockchip_pcie_rd_other_conf(struct rockchip_pcie_port *pp,
+static int rockchip_pcie_rd_other_conf(struct rockchip_pcie *rockchip,
struct pci_bus *bus, u32 devfn,
int where, int size, u32 *val)
{
busdev = PCIE_ECAM_ADDR(bus->number, PCI_SLOT(devfn),
PCI_FUNC(devfn), where);
- if (busdev & (size - 1)) {
+ if (!IS_ALIGNED(busdev, size)) {
*val = 0;
return PCIBIOS_BAD_REGISTER_NUMBER;
}
if (size == 4) {
- *val = readl(pp->reg_base + busdev);
+ *val = readl(rockchip->reg_base + busdev);
} else if (size == 2) {
- *val = readw(pp->reg_base + busdev);
+ *val = readw(rockchip->reg_base + busdev);
} else if (size == 1) {
- *val = readb(pp->reg_base + busdev);
+ *val = readb(rockchip->reg_base + busdev);
} else {
*val = 0;
return PCIBIOS_BAD_REGISTER_NUMBER;
return PCIBIOS_SUCCESSFUL;
}
-static int rockchip_pcie_wr_other_conf(struct rockchip_pcie_port *pp,
+static int rockchip_pcie_wr_other_conf(struct rockchip_pcie *rockchip,
struct pci_bus *bus, u32 devfn,
int where, int size, u32 val)
{
busdev = PCIE_ECAM_ADDR(bus->number, PCI_SLOT(devfn),
PCI_FUNC(devfn), where);
- if (busdev & (size - 1))
+ if (!IS_ALIGNED(busdev, size))
return PCIBIOS_BAD_REGISTER_NUMBER;
if (size == 4)
- writel(val, pp->reg_base + busdev);
+ writel(val, rockchip->reg_base + busdev);
else if (size == 2)
- writew(val, pp->reg_base + busdev);
+ writew(val, rockchip->reg_base + busdev);
else if (size == 1)
- writeb(val, pp->reg_base + busdev);
+ writeb(val, rockchip->reg_base + busdev);
else
return PCIBIOS_BAD_REGISTER_NUMBER;
static int rockchip_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
int size, u32 *val)
{
- struct rockchip_pcie_port *pp = bus->sysdata;
- int ret;
+ struct rockchip_pcie *rockchip = bus->sysdata;
- if (rockchip_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) {
+ if (!rockchip_pcie_valid_device(rockchip, bus, PCI_SLOT(devfn))) {
*val = 0xffffffff;
return PCIBIOS_DEVICE_NOT_FOUND;
}
- if (bus->number != pp->root_bus_nr)
- ret = rockchip_pcie_rd_other_conf(pp, bus, devfn,
- where, size, val);
- else
- ret = rockchip_pcie_rd_own_conf(pp, where, size, val);
+ if (bus->number == rockchip->root_bus_nr)
+ return rockchip_pcie_rd_own_conf(rockchip, where, size, val);
- return ret;
+ return rockchip_pcie_rd_other_conf(rockchip, bus, devfn, where, size, val);
}
static int rockchip_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
int where, int size, u32 val)
{
- struct rockchip_pcie_port *pp = bus->sysdata;
- int ret;
+ struct rockchip_pcie *rockchip = bus->sysdata;
- if (rockchip_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0)
+ if (!rockchip_pcie_valid_device(rockchip, bus, PCI_SLOT(devfn)))
return PCIBIOS_DEVICE_NOT_FOUND;
- if (bus->number != pp->root_bus_nr)
- ret = rockchip_pcie_wr_other_conf(pp, bus, devfn,
- where, size, val);
- else
- ret = rockchip_pcie_wr_own_conf(pp, where, size, val);
+ if (bus->number == rockchip->root_bus_nr)
+ return rockchip_pcie_wr_own_conf(rockchip, where, size, val);
- return ret;
+ return rockchip_pcie_wr_other_conf(rockchip, bus, devfn, where, size, val);
}
static struct pci_ops rockchip_pcie_ops = {
.write = rockchip_pcie_wr_conf,
};
+static void rockchip_pcie_set_power_limit(struct rockchip_pcie *rockchip)
+{
+ u32 status, curr, scale, power;
+
+ if (IS_ERR(rockchip->vpcie3v3))
+ return;
+
+ /*
+ * Set RC's captured slot power limit and scale if
+ * vpcie3v3 available. The default values are both zero
+ * which means the software should set these two according
+ * to the actual power supply.
+ */
+ curr = regulator_get_current_limit(rockchip->vpcie3v3);
+ if (curr > 0) {
+ scale = 3; /* 0.001x */
+ curr = curr / 1000; /* convert to mA */
+ power = (curr * 3300) / 1000; /* milliwatt */
+ while (power > PCIE_RC_CONFIG_DCR_CSPL_LIMIT) {
+ if (!scale) {
+ dev_warn(rockchip->dev, "invalid power supply\n");
+ return;
+ }
+ scale--;
+ power = power / 10;
+ }
+
+ status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_DCR);
+ status |= (power << PCIE_RC_CONFIG_DCR_CSPL_SHIFT) |
+ (scale << PCIE_RC_CONFIG_DCR_CPLS_SHIFT);
+ rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_DCR);
+ }
+}
+
/**
* rockchip_pcie_init_port - Initialize hardware
- * @port: PCIe port information
+ * @rockchip: PCIe port information
*/
-static int rockchip_pcie_init_port(struct rockchip_pcie_port *port)
+static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
{
+ struct device *dev = rockchip->dev;
int err;
u32 status;
- unsigned long timeout = jiffies + msecs_to_jiffies(1000);
+ unsigned long timeout;
- gpiod_set_value(port->ep_gpio, 0);
+ gpiod_set_value(rockchip->ep_gpio, 0);
- /* Make sure PCIe relate block is in reset state */
- err = reset_control_assert(port->phy_rst);
- if (err) {
- dev_err(port->dev, "assert phy_rst err %d\n", err);
+ err = phy_init(rockchip->phy);
+ if (err < 0) {
+ dev_err(dev, "fail to init phy, err %d\n", err);
return err;
}
- err = reset_control_assert(port->core_rst);
+
+ err = reset_control_assert(rockchip->core_rst);
if (err) {
- dev_err(port->dev, "assert core_rst err %d\n", err);
+ dev_err(dev, "assert core_rst err %d\n", err);
return err;
}
- err = reset_control_assert(port->mgmt_rst);
+
+ err = reset_control_assert(rockchip->mgmt_rst);
if (err) {
- dev_err(port->dev, "assert mgmt_rst err %d\n", err);
+ dev_err(dev, "assert mgmt_rst err %d\n", err);
return err;
}
- err = reset_control_assert(port->mgmt_sticky_rst);
+
+ err = reset_control_assert(rockchip->mgmt_sticky_rst);
if (err) {
- dev_err(port->dev, "assert mgmt_sticky_rst err %d\n", err);
+ dev_err(dev, "assert mgmt_sticky_rst err %d\n", err);
return err;
}
- err = reset_control_assert(port->pipe_rst);
+
+ err = reset_control_assert(rockchip->pipe_rst);
if (err) {
- dev_err(port->dev, "assert pipe_rst err %d\n", err);
+ dev_err(dev, "assert pipe_rst err %d\n", err);
return err;
}
- pcie_write(port, (0xf << 20) | (0x1 << 16) | PCIE_CLIENT_GEN_SEL_2 |
- (0x1 << 19) | (0x1 << 3) |
- PCIE_CLIENT_MODE_RC |
- PCIE_CLIENT_CONF_LANE_NUM(port->lanes) |
- PCIE_CLIENT_CONF_ENABLE, PCIE_CLIENT_BASE);
+ rockchip_pcie_write(rockchip,
+ PCIE_CLIENT_CONF_ENABLE |
+ PCIE_CLIENT_LINK_TRAIN_ENABLE |
+ PCIE_CLIENT_ARI_ENABLE |
+ PCIE_CLIENT_CONF_LANE_NUM(rockchip->lanes) |
+ PCIE_CLIENT_MODE_RC |
+ PCIE_CLIENT_GEN_SEL_2,
+ PCIE_CLIENT_CONFIG);
- err = reset_control_deassert(port->phy_rst);
- if (err) {
- dev_err(port->dev, "deassert phy_rst err %d\n", err);
- return err;
- }
- regmap_write(port->grf, port->pcie_conf,
- (0x3f << 17) | (0x10 << 1));
- err = -EINVAL;
- while (time_before(jiffies, timeout)) {
- regmap_read(port->grf, port->pcie_status, &status);
- if ((status & (1 << 9))) {
- dev_info(port->dev, "pll locked!\n");
- err = 0;
- break;
- }
- }
+ err = phy_power_on(rockchip->phy);
if (err) {
- dev_err(port->dev, "pll lock timeout!\n");
+ dev_err(dev, "fail to power on phy, err %d\n", err);
return err;
}
- pcie_pb_wr_cfg(port, 0x10, 0x8);
- pcie_pb_wr_cfg(port, 0x12, 0x8);
-
- err = -ETIMEDOUT;
- while (time_before(jiffies, timeout)) {
- regmap_read(port->grf, port->pcie_status, &status);
- if (!(status & (1 << 10))) {
- dev_info(port->dev, "pll output enable done!\n");
- err = 0;
- break;
- }
- }
+ /*
+ * Please don't reorder the deassert sequence of the following
+ * four reset pins.
+ */
+ err = reset_control_deassert(rockchip->mgmt_sticky_rst);
if (err) {
- dev_err(port->dev, "pll output enable timeout!\n");
+ dev_err(dev, "deassert mgmt_sticky_rst err %d\n", err);
return err;
}
- regmap_write(port->grf, port->pcie_conf,
- (0x3f << 17) | (0x10 << 1));
- err = -EINVAL;
- while (time_before(jiffies, timeout)) {
- regmap_read(port->grf, port->pcie_status, &status);
- if ((status & (1 << 9))) {
- dev_info(port->dev, "pll relocked!\n");
- err = 0;
- break;
- }
- }
+ err = reset_control_deassert(rockchip->core_rst);
if (err) {
- dev_err(port->dev, "pll relock timeout!\n");
+ dev_err(dev, "deassert core_rst err %d\n", err);
return err;
}
- err = reset_control_deassert(port->core_rst);
- if (err) {
- dev_err(port->dev, "deassert core_rst err %d\n", err);
- return err;
- }
- err = reset_control_deassert(port->mgmt_rst);
- if (err) {
- dev_err(port->dev, "deassert mgmt_rst err %d\n", err);
- return err;
- }
- err = reset_control_deassert(port->mgmt_sticky_rst);
+ err = reset_control_deassert(rockchip->mgmt_rst);
if (err) {
- dev_err(port->dev, "deassert mgmt_sticky_rst err %d\n", err);
+ dev_err(dev, "deassert mgmt_rst err %d\n", err);
return err;
}
- err = reset_control_deassert(port->pipe_rst);
+
+ err = reset_control_deassert(rockchip->pipe_rst);
if (err) {
- dev_err(port->dev, "deassert pipe_rst err %d\n", err);
+ dev_err(dev, "deassert pipe_rst err %d\n", err);
return err;
}
- pcie_write(port, 1 << 17 | 1 << 1, PCIE_CLIENT_BASE);
+ /*
+ * We need to read/write PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2 before
+ * enabling ASPM. Otherwise L1PwrOnSc and L1PwrOnVal isn't
+ * reliable and enabling ASPM doesn't work. This is a controller
+ * bug we need to work around.
+ */
+ status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2);
+ rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2);
+
+ /* Fix the transmitted FTS count desired to exit from L0s. */
+ status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL_PLC1);
+ status = (status & PCIE_CORE_CTRL_PLC1_FTS_MASK) |
+ (PCIE_CORE_CTRL_PLC1_FTS_CNT << PCIE_CORE_CTRL_PLC1_FTS_SHIFT);
+ rockchip_pcie_write(rockchip, status, PCIE_CORE_CTRL_PLC1);
+
+ rockchip_pcie_set_power_limit(rockchip);
+
+ /* Set RC's clock architecture as common clock */
+ status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);
+ status |= PCIE_RC_CONFIG_LCS_CCC;
+ rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
+
+ /* Enable Gen1 training */
+ rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE,
+ PCIE_CLIENT_CONFIG);
+
+ gpiod_set_value(rockchip->ep_gpio, 1);
- gpiod_set_value(port->ep_gpio, 1);
- err = -ETIMEDOUT;
- while (time_before(jiffies, timeout)) {
- status = pcie_read(port, PCIE_CLIENT_BASIC_STATUS1);
- if (((status >> 20) & 0x3) == 0x3) {
- dev_info(port->dev, "pcie link training gen1 pass!\n");
- err = 0;
+ /* 500ms timeout value should be enough for Gen1/2 training */
+ timeout = jiffies + msecs_to_jiffies(500);
+
+ for (;;) {
+ status = rockchip_pcie_read(rockchip,
+ PCIE_CLIENT_BASIC_STATUS1);
+ if ((status & PCIE_CLIENT_LINK_STATUS_MASK) ==
+ PCIE_CLIENT_LINK_STATUS_UP) {
+ dev_dbg(dev, "PCIe link training gen1 pass!\n");
break;
}
- }
- if (err) {
- dev_err(port->dev, "pcie link training gen1 timeout!\n");
- return err;
+
+ if (time_after(jiffies, timeout)) {
+ dev_err(dev, "PCIe link training gen1 timeout!\n");
+ return -ETIMEDOUT;
+ }
+
+ msleep(20);
}
- status = pcie_read(port, 0x9000d0);
- status |= 0x20;
- pcie_write(port, status, 0x9000d0);
- err = -ETIMEDOUT;
- while (time_before(jiffies, timeout)) {
- status = pcie_read(port, PCIE_CORE_CTRL_MGMT_BASE);
- if (((status >> 3) & 0x3) == 0x1) {
- dev_info(port->dev, "pcie link training gen2 pass!\n");
- err = 0;
+ /*
+ * Enable retrain for gen2. This should be configured only after
+ * gen1 finished.
+ */
+ status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);
+ status |= PCIE_RC_CONFIG_LCS_RETRAIN_LINK;
+ rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
+
+ timeout = jiffies + msecs_to_jiffies(500);
+ for (;;) {
+ status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL);
+ if ((status & PCIE_CORE_PL_CONF_SPEED_MASK) ==
+ PCIE_CORE_PL_CONF_SPEED_5G) {
+ dev_dbg(dev, "PCIe link training gen2 pass!\n");
break;
}
- }
- if (err)
- dev_dbg(port->dev, "pcie link training gen2 timeout, force to gen1!\n");
- if (((status >> 3) & 0x3) == 0x0)
- dev_info(port->dev, "pcie link 2.5!\n");
- if (((status >> 3) & 0x3) == 0x1)
- dev_info(port->dev, "pcie link 5.0!\n");
+ if (time_after(jiffies, timeout)) {
+ dev_dbg(dev, "PCIe link training gen2 timeout, fall back to gen1!\n");
+ break;
+ }
- status = pcie_read(port, PCIE_CORE_CTRL_MGMT_BASE);
- status = 0x1 << ((status >> 1) & 0x3);
- dev_info(port->dev, "current link width is x%d\n", status);
+ msleep(20);
+ }
- status = pcie_pb_rd_cfg(port, 0x30);
- if (!((status >> 11) & 0x1))
- dev_dbg(port->dev, "lane A is used\n");
- else
- regmap_write(port->grf, port->pcie_laneoff,
- (0x1 << 19) | (0x1 << 3));
+ /* Check the final link width from negotiated lane counter from MGMT */
+ status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL);
+ status = 0x1 << ((status & PCIE_CORE_PL_CONF_LANE_MASK) >>
+ PCIE_CORE_PL_CONF_LANE_MASK);
+ dev_dbg(dev, "current link width is x%d\n", status);
- status = pcie_pb_rd_cfg(port, 0x31);
- if (!((status >> 11) & 0x1))
- dev_dbg(port->dev, "lane B is used\n");
- else
- regmap_write(port->grf, port->pcie_laneoff,
- (0x2 << 19) | (0x2 << 3));
+ rockchip_pcie_write(rockchip, ROCKCHIP_VENDOR_ID,
+ PCIE_RC_CONFIG_VENDOR);
+ rockchip_pcie_write(rockchip,
+ PCI_CLASS_BRIDGE_PCI << PCIE_RC_CONFIG_SCC_SHIFT,
+ PCIE_RC_CONFIG_RID_CCR);
+ rockchip_pcie_write(rockchip, 0x0, PCIE_RC_BAR_CONF);
- status = pcie_pb_rd_cfg(port, 0x32);
- if (!((status >> 11) & 0x1))
- dev_dbg(port->dev, "lane C is used\n");
- else
- regmap_write(port->grf, port->pcie_laneoff,
- (0x4 << 19) | (0x4 << 3));
+ rockchip_pcie_write(rockchip,
+ (RC_REGION_0_ADDR_TRANS_L + RC_REGION_0_PASS_BITS),
+ PCIE_CORE_OB_REGION_ADDR0);
+ rockchip_pcie_write(rockchip, RC_REGION_0_ADDR_TRANS_H,
+ PCIE_CORE_OB_REGION_ADDR1);
+ rockchip_pcie_write(rockchip, 0x0080000a, PCIE_CORE_OB_REGION_DESC0);
+ rockchip_pcie_write(rockchip, 0x0, PCIE_CORE_OB_REGION_DESC1);
- status = pcie_pb_rd_cfg(port, 0x33);
- if (!((status >> 11) & 0x1))
- dev_dbg(port->dev, "lane D is used\n");
- else
- regmap_write(port->grf, port->pcie_laneoff,
- (0x8 << 19) | (0x8 << 3));
return 0;
}
-/**
- * rockchip_pcie_parse_dt - Parse Device tree
- * @port: PCIe port information
- *
- * Return: '0' on success and error value on failure
- */
-static int rockchip_pcie_parse_dt(struct rockchip_pcie_port *port)
+static irqreturn_t rockchip_pcie_subsys_irq_handler(int irq, void *arg)
{
- struct device *dev = port->dev;
- struct device_node *node = dev->of_node;
- struct resource regs;
- unsigned int pcie_conf;
- unsigned int pcie_status;
- unsigned int pcie_laneoff;
- int err;
+ struct rockchip_pcie *rockchip = arg;
+ struct device *dev = rockchip->dev;
+ u32 reg;
+ u32 sub_reg;
- err = of_address_to_resource(node, 0, ®s);
- if (err) {
- dev_err(dev, "missing \"reg\" property\n");
- return err;
- }
+ reg = rockchip_pcie_read(rockchip, PCIE_CLIENT_INT_STATUS);
+ if (reg & PCIE_CLIENT_INT_LOCAL) {
+ dev_dbg(dev, "local interrupt received\n");
+ sub_reg = rockchip_pcie_read(rockchip, PCIE_CORE_INT_STATUS);
+ if (sub_reg & PCIE_CORE_INT_PRFPE)
+ dev_dbg(dev, "parity error detected while reading from the PNP receive FIFO RAM\n");
- port->reg_base = devm_ioremap_resource(dev, ®s);
- if (IS_ERR(port->reg_base))
- return PTR_ERR(port->reg_base);
+ if (sub_reg & PCIE_CORE_INT_CRFPE)
+ dev_dbg(dev, "parity error detected while reading from the Completion Receive FIFO RAM\n");
- err = of_address_to_resource(node, 1, ®s);
- if (err) {
- dev_err(dev, "missing \"reg\" property\n");
- return err;
- }
+ if (sub_reg & PCIE_CORE_INT_RRPE)
+ dev_dbg(dev, "parity error detected while reading from replay buffer RAM\n");
- port->apb_base = devm_ioremap_resource(dev, ®s);
- if (IS_ERR(port->apb_base))
- return PTR_ERR(port->apb_base);
+ if (sub_reg & PCIE_CORE_INT_PRFO)
+ dev_dbg(dev, "overflow occurred in the PNP receive FIFO\n");
- port->grf = syscon_regmap_lookup_by_phandle(dev->of_node,
- "rockchip,grf");
- if (IS_ERR(port->grf)) {
- dev_err(dev, "Missing rockchip,grf property\n");
- return PTR_ERR(port->grf);
- }
+ if (sub_reg & PCIE_CORE_INT_CRFO)
+ dev_dbg(dev, "overflow occurred in the completion receive FIFO\n");
- if (of_property_read_u32(node, "pcie-conf", &pcie_conf)) {
- dev_err(dev, "missing pcie-conf property in node %s\n",
- node->name);
- return -EINVAL;
- }
+ if (sub_reg & PCIE_CORE_INT_RT)
+ dev_dbg(dev, "replay timer timed out\n");
- port->pcie_conf = pcie_conf;
+ if (sub_reg & PCIE_CORE_INT_RTR)
+ dev_dbg(dev, "replay timer rolled over after 4 transmissions of the same TLP\n");
- if (of_property_read_u32(node, "pcie-status", &pcie_status)) {
- dev_err(dev, "missing pcie-status property in node %s\n",
- node->name);
- return -EINVAL;
- }
+ if (sub_reg & PCIE_CORE_INT_PE)
+ dev_dbg(dev, "phy error detected on receive side\n");
- port->pcie_status = pcie_status;
+ if (sub_reg & PCIE_CORE_INT_MTR)
+ dev_dbg(dev, "malformed TLP received from the link\n");
- if (of_property_read_u32(node, "pcie-laneoff", &pcie_laneoff)) {
- dev_err(dev, "missing pcie-laneoff property in node %s\n",
- node->name);
- return -EINVAL;
- }
+ if (sub_reg & PCIE_CORE_INT_UCR)
+ dev_dbg(dev, "malformed TLP received from the link\n");
- port->pcie_laneoff = pcie_laneoff;
+ if (sub_reg & PCIE_CORE_INT_FCE)
+ dev_dbg(dev, "an error was observed in the flow control advertisements from the other side\n");
- port->lanes = 1;
- err = of_property_read_u32(node, "num-lanes", &port->lanes);
- if (!err && ((port->lanes == 0) ||
- (port->lanes == 3) ||
- (port->lanes > 4))) {
- dev_info(dev, "invalid num-lanes, default use one lane\n");
- port->lanes = 1;
- }
+ if (sub_reg & PCIE_CORE_INT_CT)
+ dev_dbg(dev, "a request timed out waiting for completion\n");
- port->phy_rst = devm_reset_control_get(dev, "phy-rst");
- if (IS_ERR(port->phy_rst)) {
- if (PTR_ERR(port->phy_rst) != -EPROBE_DEFER)
- dev_err(dev, "missing phy-rst property in node %s\n",
- node->name);
- err = PTR_ERR(port->phy_rst);
- goto err_aclk_pcie;
- }
+ if (sub_reg & PCIE_CORE_INT_UTC)
+ dev_dbg(dev, "unmapped TC error\n");
- port->core_rst = devm_reset_control_get(dev, "core-rst");
- if (IS_ERR(port->core_rst)) {
- if (PTR_ERR(port->core_rst) != -EPROBE_DEFER)
- dev_err(dev, "missing core-rst property in node %s\n",
- node->name);
- err = PTR_ERR(port->core_rst);
- goto err_aclk_pcie;
- }
+ if (sub_reg & PCIE_CORE_INT_MMVC)
+ dev_dbg(dev, "MSI mask register changes\n");
- port->mgmt_rst = devm_reset_control_get(dev, "mgmt-rst");
- if (IS_ERR(port->mgmt_rst)) {
- if (PTR_ERR(port->mgmt_rst) != -EPROBE_DEFER)
- dev_err(dev, "missing mgmt-rst property in node %s\n",
- node->name);
- err = PTR_ERR(port->mgmt_rst);
- goto err_aclk_pcie;
+ rockchip_pcie_write(rockchip, sub_reg, PCIE_CORE_INT_STATUS);
+ } else if (reg & PCIE_CLIENT_INT_PHY) {
+ dev_dbg(dev, "phy link changes\n");
+ rockchip_pcie_update_txcredit_mui(rockchip);
+ rockchip_pcie_clr_bw_int(rockchip);
}
- port->mgmt_sticky_rst = devm_reset_control_get(dev, "mgmt-sticky-rst");
- if (IS_ERR(port->mgmt_sticky_rst)) {
- if (PTR_ERR(port->mgmt_sticky_rst) != -EPROBE_DEFER)
- dev_err(dev, "missing mgmt-sticky-rst property in node %s\n",
- node->name);
- err = PTR_ERR(port->mgmt_sticky_rst);
- goto err_aclk_pcie;
- }
+ rockchip_pcie_write(rockchip, reg & PCIE_CLIENT_INT_LOCAL,
+ PCIE_CLIENT_INT_STATUS);
- port->pipe_rst = devm_reset_control_get(dev, "pipe-rst");
- if (IS_ERR(port->pipe_rst)) {
- if (PTR_ERR(port->pipe_rst) != -EPROBE_DEFER)
- dev_err(dev, "missing pipe-rst property in node %s\n",
- node->name);
- err = PTR_ERR(port->pipe_rst);
- goto err_aclk_pcie;
- }
+ return IRQ_HANDLED;
+}
- port->ep_gpio = gpiod_get(dev, "ep", GPIOD_OUT_HIGH);
- if (IS_ERR(port->ep_gpio)) {
- dev_err(dev, "missing ep-gpios property in node %s\n",
- node->name);
- return PTR_ERR(port->ep_gpio);
- }
+static irqreturn_t rockchip_pcie_client_irq_handler(int irq, void *arg)
+{
+ struct rockchip_pcie *rockchip = arg;
+ struct device *dev = rockchip->dev;
+ u32 reg;
- port->aclk_pcie = devm_clk_get(dev, "aclk_pcie");
- if (IS_ERR(port->aclk_pcie)) {
- dev_err(dev, "aclk_pcie clock not found.\n");
- return PTR_ERR(port->aclk_pcie);
- }
+ reg = rockchip_pcie_read(rockchip, PCIE_CLIENT_INT_STATUS);
+ if (reg & PCIE_CLIENT_INT_LEGACY_DONE)
+ dev_dbg(dev, "legacy done interrupt received\n");
- port->aclk_perf_pcie = devm_clk_get(dev, "aclk_perf_pcie");
- if (IS_ERR(port->aclk_perf_pcie)) {
- dev_err(dev, "aclk_perf_pcie clock not found.\n");
- return PTR_ERR(port->aclk_perf_pcie);
- }
+ if (reg & PCIE_CLIENT_INT_MSG)
+ dev_dbg(dev, "message done interrupt received\n");
- port->hclk_pcie = devm_clk_get(dev, "hclk_pcie");
- if (IS_ERR(port->hclk_pcie)) {
- dev_err(dev, "hclk_pcie clock not found.\n");
- return PTR_ERR(port->hclk_pcie);
- }
+ if (reg & PCIE_CLIENT_INT_HOT_RST)
+ dev_dbg(dev, "hot reset interrupt received\n");
- port->clk_pciephy_ref = devm_clk_get(dev, "clk_pciephy_ref");
- if (IS_ERR(port->clk_pciephy_ref)) {
- dev_err(dev, "clk_pciephy_ref clock not found.\n");
- return PTR_ERR(port->clk_pciephy_ref);
- }
+ if (reg & PCIE_CLIENT_INT_DPA)
+ dev_dbg(dev, "dpa interrupt received\n");
- err = clk_prepare_enable(port->aclk_pcie);
- if (err) {
- dev_err(dev, "Unable to enable aclk_pcie clock.\n");
- goto err_aclk_pcie;
- }
+ if (reg & PCIE_CLIENT_INT_FATAL_ERR)
+ dev_dbg(dev, "fatal error interrupt received\n");
- err = clk_prepare_enable(port->aclk_perf_pcie);
- if (err) {
- dev_err(dev, "Unable to enable aclk_perf_pcie clock.\n");
- goto err_aclk_perf_pcie;
- }
+ if (reg & PCIE_CLIENT_INT_NFATAL_ERR)
+ dev_dbg(dev, "no fatal error interrupt received\n");
- err = clk_prepare_enable(port->hclk_pcie);
- if (err) {
- dev_err(dev, "Unable to enable hclk_pcie clock.\n");
- goto err_hclk_pcie;
- }
+ if (reg & PCIE_CLIENT_INT_CORR_ERR)
+ dev_dbg(dev, "correctable error interrupt received\n");
- err = clk_prepare_enable(port->clk_pciephy_ref);
- if (err) {
- dev_err(dev, "Unable to enable hclk_pcie clock.\n");
- goto err_pciephy_ref;
- }
+ if (reg & PCIE_CLIENT_INT_PHY)
+ dev_dbg(dev, "phy interrupt received\n");
- return 0;
+ rockchip_pcie_write(rockchip, reg & (PCIE_CLIENT_INT_LEGACY_DONE |
+ PCIE_CLIENT_INT_MSG | PCIE_CLIENT_INT_HOT_RST |
+ PCIE_CLIENT_INT_DPA | PCIE_CLIENT_INT_FATAL_ERR |
+ PCIE_CLIENT_INT_NFATAL_ERR |
+ PCIE_CLIENT_INT_CORR_ERR |
+ PCIE_CLIENT_INT_PHY),
+ PCIE_CLIENT_INT_STATUS);
-err_pciephy_ref:
- clk_disable_unprepare(port->hclk_pcie);
-err_hclk_pcie:
- clk_disable_unprepare(port->aclk_perf_pcie);
-err_aclk_perf_pcie:
- clk_disable_unprepare(port->aclk_pcie);
-err_aclk_pcie:
- return err;
+ return IRQ_HANDLED;
}
-static void rockchip_pcie_msi_enable(struct rockchip_pcie_port *pp)
+static void rockchip_pcie_legacy_int_handler(struct irq_desc *desc)
{
- struct device_node *msi_node;
-
- msi_node = of_parse_phandle(pp->dev->of_node,
- "msi-parent", 0);
- if (!msi_node)
- return;
+ struct irq_chip *chip = irq_desc_get_chip(desc);
+ struct rockchip_pcie *rockchip = irq_desc_get_handler_data(desc);
+ struct device *dev = rockchip->dev;
+ u32 reg;
+ u32 hwirq;
+ u32 virq;
- pp->msi = of_pci_find_msi_chip_by_node(msi_node);
- of_node_put(msi_node);
+ chained_irq_enter(chip, desc);
- if (pp->msi)
- pp->msi->dev = pp->dev;
-}
+ reg = rockchip_pcie_read(rockchip, PCIE_CLIENT_INT_STATUS);
+ reg = (reg & PCIE_CLIENT_INTR_MASK) >> PCIE_CLIENT_INTR_SHIFT;
-static void rockchip_pcie_enable_interrupts(struct rockchip_pcie_port *pp)
-{
- pcie_write(pp, (CLIENT_INTERRUPTS << 16) &
- (~CLIENT_INTERRUPTS), PCIE_CLIENT_INT_MASK);
- pcie_write(pp, CORE_INTERRUPTS, PCIE_CORE_INT_MASK);
-}
+ while (reg) {
+ hwirq = ffs(reg) - 1;
+ reg &= ~BIT(hwirq);
-static int rockchip_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
- irq_hw_number_t hwirq)
-{
- irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
- irq_set_chip_data(irq, domain->host_data);
+ virq = irq_find_mapping(rockchip->irq_domain, hwirq);
+ if (virq)
+ generic_handle_irq(virq);
+ else
+ dev_err(dev, "unexpected IRQ, INT%d\n", hwirq);
+ }
- return 0;
+ chained_irq_exit(chip, desc);
}
-static const struct irq_domain_ops intx_domain_ops = {
- .map = rockchip_pcie_intx_map,
-};
-static int rockchip_pcie_init_irq_domain(struct rockchip_pcie_port *pp)
+/**
+ * rockchip_pcie_parse_dt - Parse Device Tree
+ * @rockchip: PCIe port information
+ *
+ * Return: '0' on success and error value on failure
+ */
+static int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip)
{
- struct device *dev = pp->dev;
+ struct device *dev = rockchip->dev;
+ struct platform_device *pdev = to_platform_device(dev);
struct device_node *node = dev->of_node;
- struct device_node *pcie_intc_node = of_get_next_child(node, NULL);
+ struct resource *regs;
+ int irq;
+ int err;
+
+ regs = platform_get_resource_byname(pdev,
+ IORESOURCE_MEM,
+ "axi-base");
+ rockchip->reg_base = devm_ioremap_resource(dev, regs);
+ if (IS_ERR(rockchip->reg_base))
+ return PTR_ERR(rockchip->reg_base);
- if (!pcie_intc_node) {
- dev_err(dev, "No PCIe Intc node found\n");
- return PTR_ERR(pcie_intc_node);
+ regs = platform_get_resource_byname(pdev,
+ IORESOURCE_MEM,
+ "apb-base");
+ rockchip->apb_base = devm_ioremap_resource(dev, regs);
+ if (IS_ERR(rockchip->apb_base))
+ return PTR_ERR(rockchip->apb_base);
+
+ rockchip->phy = devm_phy_get(dev, "pcie-phy");
+ if (IS_ERR(rockchip->phy)) {
+ if (PTR_ERR(rockchip->phy) != -EPROBE_DEFER)
+ dev_err(dev, "missing phy\n");
+ return PTR_ERR(rockchip->phy);
}
- pp->irq_domain = irq_domain_add_linear(pcie_intc_node, 4,
- &intx_domain_ops, pp);
- if (!pp->irq_domain) {
- dev_err(dev, "Failed to get a INTx IRQ domain\n");
- return PTR_ERR(pp->irq_domain);
+
+ rockchip->lanes = 1;
+ err = of_property_read_u32(node, "num-lanes", &rockchip->lanes);
+ if (!err && (rockchip->lanes == 0 ||
+ rockchip->lanes == 3 ||
+ rockchip->lanes > 4)) {
+ dev_warn(dev, "invalid num-lanes, default to use one lane\n");
+ rockchip->lanes = 1;
}
- return 0;
-}
+ rockchip->core_rst = devm_reset_control_get(dev, "core");
+ if (IS_ERR(rockchip->core_rst)) {
+ if (PTR_ERR(rockchip->core_rst) != -EPROBE_DEFER)
+ dev_err(dev, "missing core reset property in node\n");
+ return PTR_ERR(rockchip->core_rst);
+ }
-static irqreturn_t rockchip_pcie_subsys_irq_handler(int irq, void *arg)
-{
- struct rockchip_pcie_port *pp = arg;
- u32 reg;
- u32 sub_reg;
+ rockchip->mgmt_rst = devm_reset_control_get(dev, "mgmt");
+ if (IS_ERR(rockchip->mgmt_rst)) {
+ if (PTR_ERR(rockchip->mgmt_rst) != -EPROBE_DEFER)
+ dev_err(dev, "missing mgmt reset property in node\n");
+ return PTR_ERR(rockchip->mgmt_rst);
+ }
- reg = pcie_read(pp, PCIE_CLIENT_INT_STATUS);
- if (reg & LOC_INT) {
- dev_dbg(pp->dev, "local interrupt recived\n");
- sub_reg = pcie_read(pp, PCIE_CORE_INT_STATUS);
- if (sub_reg & PRFPE)
- dev_dbg(pp->dev, "Parity error detected while reading from the PNP Receive FIFO RAM\n");
+ rockchip->mgmt_sticky_rst = devm_reset_control_get(dev, "mgmt-sticky");
+ if (IS_ERR(rockchip->mgmt_sticky_rst)) {
+ if (PTR_ERR(rockchip->mgmt_sticky_rst) != -EPROBE_DEFER)
+ dev_err(dev, "missing mgmt-sticky reset property in node\n");
+ return PTR_ERR(rockchip->mgmt_sticky_rst);
+ }
- if (sub_reg & CRFPE)
- dev_dbg(pp->dev, "Parity error detected while reading from the Completion Receive FIFO RAM\n");
+ rockchip->pipe_rst = devm_reset_control_get(dev, "pipe");
+ if (IS_ERR(rockchip->pipe_rst)) {
+ if (PTR_ERR(rockchip->pipe_rst) != -EPROBE_DEFER)
+ dev_err(dev, "missing pipe reset property in node\n");
+ return PTR_ERR(rockchip->pipe_rst);
+ }
- if (sub_reg & RRPE)
- dev_dbg(pp->dev, "Parity error detected while reading from Replay Buffer RAM\n");
+ rockchip->ep_gpio = devm_gpiod_get(dev, "ep", GPIOD_OUT_HIGH);
+ if (IS_ERR(rockchip->ep_gpio)) {
+ dev_err(dev, "missing ep-gpios property in node\n");
+ return PTR_ERR(rockchip->ep_gpio);
+ }
- if (sub_reg & PRFO)
- dev_dbg(pp->dev, "Overflow occurred in the PNP Receive FIFO\n");
+ rockchip->aclk_pcie = devm_clk_get(dev, "aclk");
+ if (IS_ERR(rockchip->aclk_pcie)) {
+ dev_err(dev, "aclk clock not found\n");
+ return PTR_ERR(rockchip->aclk_pcie);
+ }
- if (sub_reg & CRFO)
- dev_dbg(pp->dev, "Overflow occurred in the Completion Receive FIFO\n");
+ rockchip->aclk_perf_pcie = devm_clk_get(dev, "aclk-perf");
+ if (IS_ERR(rockchip->aclk_perf_pcie)) {
+ dev_err(dev, "aclk_perf clock not found\n");
+ return PTR_ERR(rockchip->aclk_perf_pcie);
+ }
- if (sub_reg & RT)
- dev_dbg(pp->dev, "Replay timer timed out\n");
+ rockchip->hclk_pcie = devm_clk_get(dev, "hclk");
+ if (IS_ERR(rockchip->hclk_pcie)) {
+ dev_err(dev, "hclk clock not found\n");
+ return PTR_ERR(rockchip->hclk_pcie);
+ }
- if (sub_reg & RTR)
- dev_dbg(pp->dev, "Replay timer rolled over after 4 transmissions of the same TLP\n");
+ rockchip->clk_pcie_pm = devm_clk_get(dev, "pm");
+ if (IS_ERR(rockchip->clk_pcie_pm)) {
+ dev_err(dev, "pm clock not found\n");
+ return PTR_ERR(rockchip->clk_pcie_pm);
+ }
- if (sub_reg & PE)
- dev_dbg(pp->dev, "Phy error detected on receive side\n");
+ irq = platform_get_irq_byname(pdev, "sys");
+ if (irq < 0) {
+ dev_err(dev, "missing sys IRQ resource\n");
+ return -EINVAL;
+ }
- if (sub_reg & MTR)
- dev_dbg(pp->dev, "Malformed TLP received from the link\n");
+ err = devm_request_irq(dev, irq, rockchip_pcie_subsys_irq_handler,
+ IRQF_SHARED, "pcie-sys", rockchip);
+ if (err) {
+ dev_err(dev, "failed to request PCIe subsystem IRQ\n");
+ return err;
+ }
- if (sub_reg & UCR)
- dev_dbg(pp->dev, "Malformed TLP received from the link\n");
+ irq = platform_get_irq_byname(pdev, "legacy");
+ if (irq < 0) {
+ dev_err(dev, "missing legacy IRQ resource\n");
+ return -EINVAL;
+ }
- if (sub_reg & FCE)
- dev_dbg(pp->dev, "An error was observed in the flow control advertisements from the other side\n");
+ irq_set_chained_handler_and_data(irq,
+ rockchip_pcie_legacy_int_handler,
+ rockchip);
- if (sub_reg & CT)
- dev_dbg(pp->dev, "A request timed out waiting for completion\n");
+ irq = platform_get_irq_byname(pdev, "client");
+ if (irq < 0) {
+ dev_err(dev, "missing client IRQ resource\n");
+ return -EINVAL;
+ }
- if (sub_reg & UTC)
- dev_dbg(pp->dev, "Unmapped TC error\n");
+ err = devm_request_irq(dev, irq, rockchip_pcie_client_irq_handler,
+ IRQF_SHARED, "pcie-client", rockchip);
+ if (err) {
+ dev_err(dev, "failed to request PCIe client IRQ\n");
+ return err;
+ }
- if (sub_reg & MMVC)
- dev_dbg(pp->dev, "MSI mask register changes\n");
+ rockchip->vpcie3v3 = devm_regulator_get_optional(dev, "vpcie3v3");
+ if (IS_ERR(rockchip->vpcie3v3)) {
+ if (PTR_ERR(rockchip->vpcie3v3) == -EPROBE_DEFER)
+ return -EPROBE_DEFER;
+ dev_info(dev, "no vpcie3v3 regulator found\n");
+ }
- pcie_write(pp, sub_reg, PCIE_CORE_INT_STATUS);
+ rockchip->vpcie1v8 = devm_regulator_get_optional(dev, "vpcie1v8");
+ if (IS_ERR(rockchip->vpcie1v8)) {
+ if (PTR_ERR(rockchip->vpcie1v8) == -EPROBE_DEFER)
+ return -EPROBE_DEFER;
+ dev_info(dev, "no vpcie1v8 regulator found\n");
}
- pcie_write(pp, reg, PCIE_CLIENT_INT_STATUS);
+ rockchip->vpcie0v9 = devm_regulator_get_optional(dev, "vpcie0v9");
+ if (IS_ERR(rockchip->vpcie0v9)) {
+ if (PTR_ERR(rockchip->vpcie0v9) == -EPROBE_DEFER)
+ return -EPROBE_DEFER;
+ dev_info(dev, "no vpcie0v9 regulator found\n");
+ }
- return IRQ_HANDLED;
+ return 0;
}
-static irqreturn_t rockchip_pcie_client_irq_handler(int irq, void *arg)
+static int rockchip_pcie_set_vpcie(struct rockchip_pcie *rockchip)
{
- struct rockchip_pcie_port *pp = arg;
- u32 reg;
+ struct device *dev = rockchip->dev;
+ int err;
- reg = pcie_read(pp, PCIE_CLIENT_INT_STATUS);
- if (reg & LEGACY_DONE)
- dev_dbg(pp->dev, "legacy done interrupt recived\n");
+ if (!IS_ERR(rockchip->vpcie3v3)) {
+ err = regulator_enable(rockchip->vpcie3v3);
+ if (err) {
+ dev_err(dev, "fail to enable vpcie3v3 regulator\n");
+ goto err_out;
+ }
+ }
- if (reg & MSG_DONE)
- dev_dbg(pp->dev, "message done interrupt recived\n");
+ if (!IS_ERR(rockchip->vpcie1v8)) {
+ err = regulator_enable(rockchip->vpcie1v8);
+ if (err) {
+ dev_err(dev, "fail to enable vpcie1v8 regulator\n");
+ goto err_disable_3v3;
+ }
+ }
- if (reg & HOT_RESET)
- dev_dbg(pp->dev, "hot reset interrupt recived\n");
+ if (!IS_ERR(rockchip->vpcie0v9)) {
+ err = regulator_enable(rockchip->vpcie0v9);
+ if (err) {
+ dev_err(dev, "fail to enable vpcie0v9 regulator\n");
+ goto err_disable_1v8;
+ }
+ }
- if (reg & DPA_INT)
- dev_dbg(pp->dev, "dpa interrupt recived\n");
+ return 0;
- if (reg & FATAL_ERR)
- dev_dbg(pp->dev, "fatal error interrupt recived\n");
+err_disable_1v8:
+ if (!IS_ERR(rockchip->vpcie1v8))
+ regulator_disable(rockchip->vpcie1v8);
+err_disable_3v3:
+ if (!IS_ERR(rockchip->vpcie3v3))
+ regulator_disable(rockchip->vpcie3v3);
+err_out:
+ return err;
+}
- if (reg & DPA_INT)
- dev_dbg(pp->dev, "no fatal error interrupt recived\n");
+static void rockchip_pcie_enable_interrupts(struct rockchip_pcie *rockchip)
+{
+ rockchip_pcie_write(rockchip, (PCIE_CLIENT_INT_CLI << 16) &
+ (~PCIE_CLIENT_INT_CLI), PCIE_CLIENT_INT_MASK);
+ rockchip_pcie_write(rockchip, (u32)(~PCIE_CORE_INT),
+ PCIE_CORE_INT_MASK);
- if (reg & CORR_ERR)
- dev_dbg(pp->dev, "correctable error interrupt recived\n");
+ rockchip_pcie_enable_bw_int(rockchip);
+}
- pcie_write(pp, reg, PCIE_CLIENT_INT_STATUS);
+static int rockchip_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
+ irq_hw_number_t hwirq)
+{
+ irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
+ irq_set_chip_data(irq, domain->host_data);
- return IRQ_HANDLED;
+ return 0;
}
-static irqreturn_t rockchip_pcie_legacy_int_handler(int irq, void *arg)
+static const struct irq_domain_ops intx_domain_ops = {
+ .map = rockchip_pcie_intx_map,
+};
+
+static int rockchip_pcie_init_irq_domain(struct rockchip_pcie *rockchip)
{
- struct rockchip_pcie_port *pp = arg;
- u32 reg;
+ struct device *dev = rockchip->dev;
+ struct device_node *intc = of_get_next_child(dev->of_node, NULL);
- reg = pcie_read(pp, PCIE_CLIENT_INT_STATUS);
- reg = (reg & ROCKCHIP_PCIE_RPIFR1_INTR_MASK) >>
- ROCKCHIP_PCIE_RPIFR1_INTR_SHIFT;
- generic_handle_irq(irq_find_mapping(pp->irq_domain, ffs(reg)));
+ if (!intc) {
+ dev_err(dev, "missing child interrupt-controller node\n");
+ return -EINVAL;
+ }
- pcie_write(pp, reg, PCIE_CLIENT_INT_STATUS);
- return IRQ_HANDLED;
+ rockchip->irq_domain = irq_domain_add_linear(intc, 4,
+ &intx_domain_ops, rockchip);
+ if (!rockchip->irq_domain) {
+ dev_err(dev, "failed to get a INTx IRQ domain\n");
+ return -EINVAL;
+ }
+
+ return 0;
}
-static int rockchip_pcie_prog_ob_atu(struct rockchip_pcie_port *pp,
- int region_no,
- int type, u8 num_pass_bits,
+static int rockchip_pcie_prog_ob_atu(struct rockchip_pcie *rockchip,
+ int region_no, int type, u8 num_pass_bits,
u32 lower_addr, u32 upper_addr)
{
- u32 ob_addr_0 = 0;
- u32 ob_addr_1 = 0;
- u32 ob_desc_0 = 0;
- u32 ob_desc_1 = 0;
- void __iomem *aw_base;
+ u32 ob_addr_0;
+ u32 ob_addr_1;
+ u32 ob_desc_0;
+ u32 aw_offset;
- if (!pp)
- return -EINVAL;
if (region_no >= MAX_AXI_WRAPPER_REGION_NUM)
return -EINVAL;
- if ((num_pass_bits + 1) < 8)
+ if (num_pass_bits + 1 < 8)
return -EINVAL;
if (num_pass_bits > 63)
return -EINVAL;
}
if (region_no != 0) {
if (AXI_REGION_SIZE < (2ULL << num_pass_bits))
- return -EINVAL;
+ return -EINVAL;
}
- aw_base = pp->apb_base + PCIE_CORE_AXI_CONF_BASE;
- aw_base += (region_no << OB_REG_SIZE_SHIFT);
-
- ob_addr_0 = (ob_addr_0 &
- ~0x0000003fU) | (num_pass_bits &
- 0x0000003fU);
- ob_addr_0 = (ob_addr_0 &
- ~0xffffff00U) | (lower_addr & 0xffffff00U);
+
+ aw_offset = (region_no << OB_REG_SIZE_SHIFT);
+
+ ob_addr_0 = num_pass_bits & PCIE_CORE_OB_REGION_ADDR0_NUM_BITS;
+ ob_addr_0 |= lower_addr & PCIE_CORE_OB_REGION_ADDR0_LO_ADDR;
ob_addr_1 = upper_addr;
ob_desc_0 = (1 << 23 | type);
- writel(ob_addr_0, aw_base);
- writel(ob_addr_1, aw_base + 0x4);
- writel(ob_desc_0, aw_base + 0x8);
- writel(ob_desc_1, aw_base + 0xc);
+ rockchip_pcie_write(rockchip, ob_addr_0,
+ PCIE_CORE_OB_REGION_ADDR0 + aw_offset);
+ rockchip_pcie_write(rockchip, ob_addr_1,
+ PCIE_CORE_OB_REGION_ADDR1 + aw_offset);
+ rockchip_pcie_write(rockchip, ob_desc_0,
+ PCIE_CORE_OB_REGION_DESC0 + aw_offset);
+ rockchip_pcie_write(rockchip, 0,
+ PCIE_CORE_OB_REGION_DESC1 + aw_offset);
return 0;
}
-static int rockchip_pcie_prog_ib_atu(struct rockchip_pcie_port *pp,
- int region_no,
- u8 num_pass_bits,
- u32 lower_addr,
- u32 upper_addr)
+static int rockchip_pcie_prog_ib_atu(struct rockchip_pcie *rockchip,
+ int region_no, u8 num_pass_bits,
+ u32 lower_addr, u32 upper_addr)
{
- u32 ib_addr_0 = 0;
- u32 ib_addr_1 = 0;
- void __iomem *aw_base;
+ u32 ib_addr_0;
+ u32 ib_addr_1;
+ u32 aw_offset;
- if (!pp)
- return -EINVAL;
if (region_no > MAX_AXI_IB_ROOTPORT_REGION_NUM)
return -EINVAL;
- if ((num_pass_bits + 1) < MIN_AXI_ADDR_BITS_PASSED)
+ if (num_pass_bits + 1 < MIN_AXI_ADDR_BITS_PASSED)
return -EINVAL;
if (num_pass_bits > 63)
return -EINVAL;
- aw_base = pp->apb_base + PCIE_CORE_AXI_INBOUND_BASE;
- aw_base += (region_no << IB_ROOT_PORT_REG_SIZE_SHIFT);
- ib_addr_0 = (ib_addr_0 &
- ~0x0000003fU) | (num_pass_bits &
- 0x0000003fU);
-
- ib_addr_0 = (ib_addr_0 & ~0xffffff00U) |
- ((lower_addr << 8) & 0xffffff00U);
+
+ aw_offset = (region_no << IB_ROOT_PORT_REG_SIZE_SHIFT);
+
+ ib_addr_0 = num_pass_bits & PCIE_CORE_IB_REGION_ADDR0_NUM_BITS;
+ ib_addr_0 |= (lower_addr << 8) & PCIE_CORE_IB_REGION_ADDR0_LO_ADDR;
ib_addr_1 = upper_addr;
- writel(ib_addr_0, aw_base);
- writel(ib_addr_1, aw_base + 0x4);
+
+ rockchip_pcie_write(rockchip, ib_addr_0, PCIE_RP_IB_ADDR0 + aw_offset);
+ rockchip_pcie_write(rockchip, ib_addr_1, PCIE_RP_IB_ADDR1 + aw_offset);
return 0;
}
static int rockchip_pcie_probe(struct platform_device *pdev)
{
- struct rockchip_pcie_port *port;
+ struct rockchip_pcie *rockchip;
struct device *dev = &pdev->dev;
struct pci_bus *bus, *child;
struct resource_entry *win;
+ resource_size_t io_base;
+ struct resource *mem;
+ struct resource *io;
+ phys_addr_t io_bus_addr = 0;
+ u32 io_size;
+ phys_addr_t mem_bus_addr = 0;
+ u32 mem_size = 0;
int reg_no;
- int err = 0;
- int irq;
+ int err;
+ int offset;
+
LIST_HEAD(res);
if (!dev->of_node)
return -ENODEV;
- port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
- if (!port)
+ rockchip = devm_kzalloc(dev, sizeof(*rockchip), GFP_KERNEL);
+ if (!rockchip)
return -ENOMEM;
- irq = platform_get_irq_byname(pdev, "pcie-sys");
- if (irq < 0) {
- dev_err(dev, "missing pcie_sys IRQ resource\n");
- return -EINVAL;
- }
- err = devm_request_irq(dev, irq, rockchip_pcie_subsys_irq_handler,
- IRQF_SHARED, "pcie-sys", port);
- if (err) {
- dev_err(dev, "failed to request pcie subsystem irq\n");
+ rockchip->dev = dev;
+
+ err = rockchip_pcie_parse_dt(rockchip);
+ if (err)
return err;
- }
- port->irq = platform_get_irq_byname(pdev, "pcie-legacy");
- if (port->irq < 0) {
- dev_err(dev, "missing pcie_legacy IRQ resource\n");
- return -EINVAL;
+ err = clk_prepare_enable(rockchip->aclk_pcie);
+ if (err) {
+ dev_err(dev, "unable to enable aclk_pcie clock\n");
+ goto err_aclk_pcie;
}
- err = devm_request_irq(dev, port->irq,
- rockchip_pcie_legacy_int_handler,
- IRQF_SHARED,
- "pcie-legacy",
- port);
+
+ err = clk_prepare_enable(rockchip->aclk_perf_pcie);
if (err) {
- dev_err(&pdev->dev, "failed to request pcie-legacy irq\n");
- return err;
+ dev_err(dev, "unable to enable aclk_perf_pcie clock\n");
+ goto err_aclk_perf_pcie;
}
- irq = platform_get_irq_byname(pdev, "pcie-client");
- if (irq < 0) {
- dev_err(dev, "missing pcie-client IRQ resource\n");
- return -EINVAL;
+ err = clk_prepare_enable(rockchip->hclk_pcie);
+ if (err) {
+ dev_err(dev, "unable to enable hclk_pcie clock\n");
+ goto err_hclk_pcie;
}
- err = devm_request_irq(dev, irq, rockchip_pcie_client_irq_handler,
- IRQF_SHARED, "pcie-client", port);
+
+ err = clk_prepare_enable(rockchip->clk_pcie_pm);
if (err) {
- dev_err(dev, "failed to request pcie client irq\n");
- return err;
+ dev_err(dev, "unable to enable hclk_pcie clock\n");
+ goto err_pcie_pm;
}
- port->dev = dev;
- err = rockchip_pcie_parse_dt(port);
+ err = rockchip_pcie_set_vpcie(rockchip);
if (err) {
- dev_err(dev, "Parsing DT failed\n");
- return err;
+ dev_err(dev, "failed to set vpcie regulator\n");
+ goto err_set_vpcie;
}
- err = rockchip_pcie_init_port(port);
+ err = rockchip_pcie_init_port(rockchip);
if (err)
- return err;
+ goto err_vpcie;
- platform_set_drvdata(pdev, port);
+ platform_set_drvdata(pdev, rockchip);
- rockchip_pcie_enable_interrupts(port);
- if (!IS_ENABLED(CONFIG_PCI_MSI)) {
- err = rockchip_pcie_init_irq_domain(port);
- if (err < 0)
- return err;
- }
+ rockchip_pcie_enable_interrupts(rockchip);
+
+ err = rockchip_pcie_init_irq_domain(rockchip);
+ if (err < 0)
+ goto err_vpcie;
err = of_pci_get_host_bridge_resources(dev->of_node, 0, 0xff,
- &res, &port->io_base);
+ &res, &io_base);
if (err)
- return err;
+ goto err_vpcie;
+
+ err = devm_request_pci_bus_resources(dev, &res);
+ if (err)
+ goto err_vpcie;
+
/* Get the I/O and memory ranges from DT */
+ io_size = 0;
resource_list_for_each_entry(win, &res) {
switch (resource_type(win->res)) {
case IORESOURCE_IO:
- port->io = win->res;
- port->io->name = "I/O";
- port->io_size = resource_size(port->io);
- port->io_bus_addr = port->io->start - win->offset;
- err = pci_remap_iospace(port->io, port->io_base);
+ io = win->res;
+ io->name = "I/O";
+ io_size = resource_size(io);
+ io_bus_addr = io->start - win->offset;
+ err = pci_remap_iospace(io, io_base);
if (err) {
- dev_warn(port->dev, "error %d: failed to map resource %pR\n",
- err, port->io);
+ dev_warn(dev, "error %d: failed to map resource %pR\n",
+ err, io);
continue;
}
break;
case IORESOURCE_MEM:
- port->mem = win->res;
- port->mem->name = "MEM";
- port->mem_size = resource_size(port->mem);
- port->mem_bus_addr = port->mem->start - win->offset;
- break;
- case 0:
- port->cfg = win->res;
+ mem = win->res;
+ mem->name = "MEM";
+ mem_size = resource_size(mem);
+ mem_bus_addr = mem->start - win->offset;
break;
case IORESOURCE_BUS:
- port->busn = win->res;
+ rockchip->root_bus_nr = win->res->start;
break;
default:
continue;
}
}
- pcie_write(port, 0x6040000, PCIE_RC_CONFIG_BASE + 0x8);
- pcie_write(port, 0x0, PCIE_CORE_CTRL_MGMT_BASE + 0x300);
-
- pcie_write(port, (RC_REGION_0_ADDR_TRANS_L + RC_REGION_0_PASS_BITS),
- PCIE_CORE_AXI_CONF_BASE);
- pcie_write(port, RC_REGION_0_ADDR_TRANS_H,
- PCIE_CORE_AXI_CONF_BASE + 0x4);
- pcie_write(port, 0x0080000a, PCIE_CORE_AXI_CONF_BASE + 0x8);
- pcie_write(port, 0x00000000, PCIE_CORE_AXI_CONF_BASE + 0xc);
-
- for (reg_no = 0; reg_no < (port->mem_size >> 20); reg_no++) {
- err = rockchip_pcie_prog_ob_atu(port, reg_no + 1,
- AXI_WRAPPER_MEM_WRITE,
- 20 - 1,
- port->mem_bus_addr +
+ if (mem_size) {
+ for (reg_no = 0; reg_no < (mem_size >> 20); reg_no++) {
+ err = rockchip_pcie_prog_ob_atu(rockchip, reg_no + 1,
+ AXI_WRAPPER_MEM_WRITE,
+ 20 - 1,
+ mem_bus_addr +
(reg_no << 20),
- 0);
- if (err) {
- dev_err(dev, "Program RC outbound atu failed\n");
- return err;
+ 0);
+ if (err) {
+ dev_err(dev, "program RC mem outbound ATU failed\n");
+ goto err_vpcie;
+ }
}
}
- err = rockchip_pcie_prog_ib_atu(port, 2, 32 - 1, 0x0, 0);
+ err = rockchip_pcie_prog_ib_atu(rockchip, 2, 32 - 1, 0x0, 0);
if (err) {
- dev_err(dev, "Program RC inbound atu failed\n");
- return err;
+ dev_err(dev, "program RC mem inbound ATU failed\n");
+ goto err_vpcie;
}
- rockchip_pcie_msi_enable(port);
+ offset = mem_size >> 20;
- port->root_bus_nr = port->busn->start;
- if (IS_ENABLED(CONFIG_PCI_MSI)) {
- bus = pci_scan_root_bus_msi(port->dev, port->root_bus_nr,
- &rockchip_pcie_ops, port, &res,
- port->msi);
- } else {
- bus = pci_scan_root_bus(&pdev->dev, 0,
- &rockchip_pcie_ops, port, &res);
+ if (io_size) {
+ for (reg_no = 0; reg_no < (io_size >> 20); reg_no++) {
+ err = rockchip_pcie_prog_ob_atu(rockchip,
+ reg_no + 1 + offset,
+ AXI_WRAPPER_IO_WRITE,
+ 20 - 1,
+ io_bus_addr +
+ (reg_no << 20),
+ 0);
+ if (err) {
+ dev_err(dev, "program RC io outbound ATU failed\n");
+ goto err_vpcie;
+ }
+ }
}
- if (!bus)
- return -ENOMEM;
- if (!pci_has_flag(PCI_PROBE_ONLY)) {
- pci_bus_size_bridges(bus);
- pci_bus_assign_resources(bus);
- list_for_each_entry(child, &bus->children, node)
- pcie_bus_configure_settings(child);
+ bus = pci_scan_root_bus(&pdev->dev, 0, &rockchip_pcie_ops, rockchip, &res);
+ if (!bus) {
+ err = -ENOMEM;
+ goto err_vpcie;
}
- pci_bus_add_devices(bus);
+ pci_bus_size_bridges(bus);
+ pci_bus_assign_resources(bus);
+ list_for_each_entry(child, &bus->children, node)
+ pcie_bus_configure_settings(child);
- return err;
-}
+ pci_bus_add_devices(bus);
-static int rockchip_pcie_remove(struct platform_device *pdev)
-{
- struct rockchip_pcie_port *port = platform_get_drvdata(pdev);
+ dev_warn(dev, "only 32-bit config accesses supported; smaller writes may corrupt adjacent RW1C fields\n");
- clk_disable_unprepare(port->hclk_pcie);
- clk_disable_unprepare(port->aclk_perf_pcie);
- clk_disable_unprepare(port->aclk_pcie);
- clk_disable_unprepare(port->clk_pciephy_ref);
+ return err;
- return 0;
+err_vpcie:
+ if (!IS_ERR(rockchip->vpcie3v3))
+ regulator_disable(rockchip->vpcie3v3);
+ if (!IS_ERR(rockchip->vpcie1v8))
+ regulator_disable(rockchip->vpcie1v8);
+ if (!IS_ERR(rockchip->vpcie0v9))
+ regulator_disable(rockchip->vpcie0v9);
+err_set_vpcie:
+ clk_disable_unprepare(rockchip->clk_pcie_pm);
+err_pcie_pm:
+ clk_disable_unprepare(rockchip->hclk_pcie);
+err_hclk_pcie:
+ clk_disable_unprepare(rockchip->aclk_perf_pcie);
+err_aclk_perf_pcie:
+ clk_disable_unprepare(rockchip->aclk_pcie);
+err_aclk_pcie:
+ return err;
}
static const struct of_device_id rockchip_pcie_of_match[] = {
.driver = {
.name = "rockchip-pcie",
.of_match_table = rockchip_pcie_of_match,
- .suppress_bind_attrs = true,
},
.probe = rockchip_pcie_probe,
- .remove = rockchip_pcie_remove,
-};
-module_platform_driver(rockchip_pcie_driver);
-MODULE_AUTHOR("Rockchip Inc");
-MODULE_DESCRIPTION("Rockchip AXI PCIe driver");
-MODULE_LICENSE("GPL v2");
+};
+builtin_platform_driver(rockchip_pcie_driver);
projects / firefly-linux-kernel-4.4.55.git / blobdiff