8723BU: Update 8723BU wifi driver to version v4.3.16_14189.20150519_BTCOEX2015119...

[firefly-linux-kernel-4.4.55.git] / drivers / net / wireless / rockchip_wlan / rtl8723bu / hal / OUTSRC / phydm_RegDefine11N.h

diff --git a/drivers/net/wireless/rockchip_wlan/rtl8723bu/hal/OUTSRC/phydm_RegDefine11N.h b/drivers/net/wireless/rockchip_wlan/rtl8723bu/hal/OUTSRC/phydm_RegDefine11N.h
index 9d07509f6febf88fad8a138621b60441f49490d7..374943d3ad78b20b36445490b757bb03c1147230 100755 (executable)
--- a/drivers/net/wireless/rockchip_wlan/rtl8723bu/hal/OUTSRC/phydm_RegDefine11N.h
+++ b/drivers/net/wireless/rockchip_wlan/rtl8723bu/hal/OUTSRC/phydm_RegDefine11N.h
@@ -44,16 +44,16 @@
 #define        ODM_REG_RF_PIN_11N                              0x804\r
 #define        ODM_REG_PSD_CTRL_11N                            0x808\r
 #define        ODM_REG_TX_ANT_CTRL_11N                 0x80C\r
-#define        ODM_REG_BB_PWR_SAV5_11N         0x818\r
+#define        ODM_REG_BB_PWR_SAV5_11N                 0x818\r
 #define        ODM_REG_CCK_RPT_FORMAT_11N              0x824\r
 #define        ODM_REG_CCK_RPT_FORMAT_11N_B    0x82C\r
 #define        ODM_REG_RX_DEFUALT_A_11N                0x858\r
 #define        ODM_REG_RX_DEFUALT_B_11N                0x85A\r
-#define        ODM_REG_BB_PWR_SAV3_11N         0x85C\r
+#define        ODM_REG_BB_PWR_SAV3_11N                 0x85C\r
 #define        ODM_REG_ANTSEL_CTRL_11N                 0x860\r
 #define        ODM_REG_RX_ANT_CTRL_11N                 0x864\r
 #define        ODM_REG_PIN_CTRL_11N                            0x870\r
-#define        ODM_REG_BB_PWR_SAV1_11N         0x874\r
+#define        ODM_REG_BB_PWR_SAV1_11N                 0x874\r
 #define        ODM_REG_ANTSEL_PATH_11N                 0x878\r
 #define        ODM_REG_BB_3WIRE_11N                    0x88C\r
 #define        ODM_REG_SC_CNT_11N                              0x8C4\r
@@ -66,8 +66,11 @@
 #define        ODM_REG_NHM_CNT_11N                             0x8d8\r
 //PAGE 9\r
 #define        ODM_REG_DBG_RPT_11N                             0x908\r
+#define        ODM_REG_BB_TX_PATH_11N                  0x90c\r
 #define        ODM_REG_ANT_MAPPING1_11N                0x914\r
 #define        ODM_REG_ANT_MAPPING2_11N                0x918\r
+#define        ODM_REG_EDCCA_DOWN_OPT_11N      0x948\r
+\r
 //PAGE A\r
 #define        ODM_REG_CCK_ANTDIV_PARA1_11N    0xA00\r
 #define        ODM_REG_CCK_CCA_11N                             0xA0A\r
@@ -86,7 +89,7 @@
 #define        ODM_REG_CCK_FA_MSB_11N                  0xA58\r
 #define        ODM_REG_CCK_FA_LSB_11N                  0xA5C\r
 #define        ODM_REG_CCK_CCA_CNT_11N                 0xA60\r
-#define        ODM_REG_BB_PWR_SAV4_11N         0xA74\r
+#define        ODM_REG_BB_PWR_SAV4_11N                 0xA74\r
 //PAGE B\r
 #define        ODM_REG_LNA_SWITCH_11N                  0xB2C\r
 #define        ODM_REG_PATH_SWITCH_11N                 0xB30\r
@@ -98,9 +101,9 @@
 #define        ODM_REG_BB_RX_PATH_11N                  0xC04\r
 #define        ODM_REG_TRMUX_11N                               0xC08\r
 #define        ODM_REG_OFDM_FA_RSTC_11N                0xC0C\r
-#define        ODM_REG_RXIQI_MATRIX_11N                        0xC14\r
+#define        ODM_REG_RXIQI_MATRIX_11N                0xC14\r
 #define        ODM_REG_TXIQK_MATRIX_LSB1_11N   0xC4C\r
-#define        ODM_REG_IGI_A_11N                                       0xC50\r
+#define        ODM_REG_IGI_A_11N                               0xC50\r
 #define        ODM_REG_ANTDIV_PARA2_11N                0xC54\r
 #define        ODM_REG_IGI_B_11N                                       0xC58\r
 #define        ODM_REG_ANTDIV_PARA3_11N                0xC5C\r
@@ -129,6 +132,7 @@
 #define        ODM_REG_TXAGC_A_MCS4_7_11N              0xE14\r
 #define        ODM_REG_TXAGC_A_MCS8_11_11N     0xE18\r
 #define        ODM_REG_TXAGC_A_MCS12_15_11N    0xE1C\r
+#define        DOM_REG_EDCCA_DCNF_11N                  0xE24\r
 #define        ODM_REG_FPGA0_IQK_11N                   0xE28\r
 #define        ODM_REG_TXIQK_TONE_A_11N                0xE30\r
 #define        ODM_REG_RXIQK_TONE_A_11N                0xE34\r
@@ -167,14 +171,15 @@
 #define        ODM_REG_EDCA_BK_11N                             0x50C\r
 #define        ODM_REG_TXPAUSE_11N                             0x522\r
 #define        ODM_REG_RESP_TX_11N                             0x6D8\r
-#define        ODM_REG_ANT_TRAIN_PARA1_11N             0x7b0\r
-#define        ODM_REG_ANT_TRAIN_PARA2_11N             0x7b4\r
+#define        ODM_REG_ANT_TRAIN_PARA1_11N     0x7b0\r
+#define        ODM_REG_ANT_TRAIN_PARA2_11N     0x7b4\r
 \r
 \r
 //DIG Related\r
 #define        ODM_BIT_IGI_11N                                 0x0000007F\r
 #define        ODM_BIT_CCK_RPT_FORMAT_11N              BIT9\r
 #define        ODM_BIT_BB_RX_PATH_11N                  0xF\r
+#define        ODM_BIT_BB_TX_PATH_11N                  0xF\r
 #define        ODM_BIT_BB_ATC_11N                              BIT11\r
 \r
 #endif\r