//============================================================\r
// include files\r
//============================================================\r
+#include "phydm_pre_define.h"\r
#include "phydm_DIG.h"\r
#include "phydm_EdcaTurboCheck.h"\r
#include "phydm_PathDiv.h"\r
+#include "phydm_AntDiv.h"\r
+#include "phydm_AntDect.h"\r
#include "phydm_DynamicBBPowerSaving.h"\r
#include "phydm_RaInfo.h"\r
#include "phydm_DynamicTxPower.h"\r
#include "phydm_ACS.h"\r
#include "phydm_PowerTracking.h"\r
#include "PhyDM_Adaptivity.h"\r
+\r
+#if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_AP))\r
+#if (RTL8814A_SUPPORT == 1)\r
+#include "rtl8814a/PhyDM_IQK_8814A.h"\r
+#endif\r
+#endif\r
+\r
+#if (DM_ODM_SUPPORT_TYPE & (ODM_CE))\r
#include "phydm_NoiseMonitor.h"\r
+#endif\r
#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN))\r
+#include "phydm_beamforming.h"\r
#include "phydm_RXHP.h"\r
#endif\r
\r
//\r
\r
\r
-\r
-//\r
-// Antenna Switch Relative Definition.\r
-//\r
-\r
-//\r
-// 20100503 Joseph:\r
-// Add new function SwAntDivCheck8192C().\r
-// This is the main function of Antenna diversity function before link.\r
-// Mainly, it just retains last scan result and scan again.\r
-// After that, it compares the scan result to see which one gets better RSSI.\r
-// It selects antenna with better receiving power and returns better scan result.\r
-//\r
+//For SW AntDiv, PathDiv, 8192C AntDiv joint use\r
#define TP_MODE 0\r
#define RSSI_MODE 1\r
+\r
#define TRAFFIC_LOW 0\r
#define TRAFFIC_HIGH 1\r
+#define TRAFFIC_UltraLOW 2\r
+\r
#define NONE 0\r
\r
\r
-//============================================================\r
-//3 Tx Power Tracking\r
-//3============================================================\r
-\r
-\r
-//============================================================\r
-//3 PSD Handler\r
-//3============================================================\r
-\r
-#define AFH_PSD 1 //0:normal PSD scan, 1: only do 20 pts PSD\r
-#define MODE_40M 0 //0:20M, 1:40M\r
-#define PSD_TH2 3 \r
-#define PSD_CHMIN 20 // Minimum channel number for BT AFH\r
-#define SIR_STEP_SIZE 3\r
-#define Smooth_Size_1 5\r
-#define Smooth_TH_1 3\r
-#define Smooth_Size_2 10\r
-#define Smooth_TH_2 4\r
-#define Smooth_Size_3 20\r
-#define Smooth_TH_3 4\r
-#define Smooth_Step_Size 5\r
-#define Adaptive_SIR 1\r
-#if(RTL8723_FPGA_VERIFICATION == 1)\r
-#define PSD_RESCAN 1\r
-#else\r
-#define PSD_RESCAN 4\r
-#endif\r
-#define PSD_SCAN_INTERVAL 700 //ms\r
-\r
\r
\r
//8723A High Power IGI Setting\r
#define DM_DIG_HIGH_PWR_THRESHOLD 0x3a\r
#define DM_DIG_LOW_PWR_THRESHOLD 0x14\r
\r
-//ANT Test\r
-#define ANTTESTALL 0x00 //Ant A or B will be Testing \r
-#define ANTTESTA 0x01 //Ant A will be Testing \r
-#define ANTTESTB 0x02 //Ant B will be testing\r
-\r
-//for 8723A Ant Definition--2012--06--07 due to different IC may be different ANT define\r
-#define MAIN_ANT 1 //Ant A or Ant Main\r
-#define AUX_ANT 2 //AntB or Ant Aux\r
-#define MAX_ANT 3 // 3 for AP using\r
-\r
\r
-//Antenna Diversity Type\r
-#define SW_ANTDIV 0\r
-#define HW_ANTDIV 1\r
//============================================================\r
// structure and define\r
//============================================================\r
\r
#endif\r
\r
-//Remove DIG by Yuchen\r
-\r
-//Remoce BB power saving by Yuchn\r
-\r
-//Remove DIG by yuchen\r
-\r
typedef struct _Dynamic_Primary_CCA{\r
u1Byte PriCCA_flag;\r
u1Byte intf_flag;\r
u1Byte DupRTS_flag;\r
u1Byte Monitor_flag;\r
u1Byte CH_offset;\r
- u1Byte MF_state;\r
+ u1Byte MF_state;\r
}Pri_CCA_T, *pPri_CCA_T;\r
\r
-//Remove RA_T,*pRA_T by RS_James\r
-\r
-typedef struct _RX_High_Power_\r
-{\r
- u1Byte RXHP_flag;\r
- u1Byte PSD_func_trigger;\r
- u1Byte PSD_bitmap_RXHP[80];\r
- u1Byte Pre_IGI;\r
- u1Byte Cur_IGI;\r
- u1Byte Pre_pw_th;\r
- u1Byte Cur_pw_th;\r
- BOOLEAN First_time_enter;\r
- BOOLEAN RXHP_enable;\r
- u1Byte TP_Mode;\r
- RT_TIMER PSDTimer;\r
-#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) \r
- #if USE_WORKITEM\r
- RT_WORK_ITEM PSDTimeWorkitem;\r
- #endif\r
-#endif\r
-\r
-}RXHP_T, *pRXHP_T;\r
- \r
-#if(DM_ODM_SUPPORT_TYPE & (ODM_CE))\r
-#define ASSOCIATE_ENTRY_NUM 32 // Max size of AsocEntry[].\r
-#define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM\r
-\r
-#elif(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))\r
-#define ASSOCIATE_ENTRY_NUM NUM_STAT\r
-#define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM+1\r
-\r
-#else\r
-//\r
-// 2012/01/12 MH Revise for compatiable with other SW team. \r
-// 0 is for STA 1-n is for AP clients.\r
-//\r
-#define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM+1// Default port only one\r
-#endif\r
\r
-//#ifdef CONFIG_ANTENNA_DIVERSITY\r
-// This indicates two different the steps. \r
-// In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air.\r
-// In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK\r
-// with original RSSI to determine if it is necessary to switch antenna.\r
-#define SWAW_STEP_PEAK 0\r
-#define SWAW_STEP_DETERMINE 1\r
-\r
-#define TP_MODE 0\r
-#define RSSI_MODE 1\r
-#define TRAFFIC_LOW 0\r
-#define TRAFFIC_HIGH 1\r
-#define TRAFFIC_UltraLOW 2\r
-\r
-typedef struct _SW_Antenna_Switch_\r
-{\r
- u1Byte Double_chk_flag;\r
- u1Byte try_flag;\r
- s4Byte PreRSSI;\r
- u1Byte CurAntenna;\r
- u1Byte PreAntenna;\r
- u1Byte RSSI_Trying;\r
- u1Byte TestMode;\r
- u1Byte bTriggerAntennaSwitch;\r
- u1Byte SelectAntennaMap;\r
- u1Byte RSSI_target; \r
- u1Byte reset_idx;\r
- u2Byte Single_Ant_Counter;\r
- u2Byte Dual_Ant_Counter;\r
- u2Byte Aux_FailDetec_Counter;\r
- u2Byte Retry_Counter;\r
-\r
- // Before link Antenna Switch check\r
- u1Byte SWAS_NoLink_State;\r
- u4Byte SWAS_NoLink_BK_Reg860;\r
- u4Byte SWAS_NoLink_BK_Reg92c;\r
- u4Byte SWAS_NoLink_BK_Reg948;\r
- BOOLEAN ANTA_ON; //To indicate Ant A is or not\r
- BOOLEAN ANTB_ON; //To indicate Ant B is on or not\r
- BOOLEAN Pre_Aux_FailDetec;\r
- BOOLEAN RSSI_AntDect_bResult; \r
- u1Byte Ant5G;\r
- u1Byte Ant2G;\r
-\r
- s4Byte RSSI_sum_A;\r
- s4Byte RSSI_sum_B;\r
- s4Byte RSSI_cnt_A;\r
- s4Byte RSSI_cnt_B;\r
-\r
- u8Byte lastTxOkCnt;\r
- u8Byte lastRxOkCnt;\r
- u8Byte TXByteCnt_A;\r
- u8Byte TXByteCnt_B;\r
- u8Byte RXByteCnt_A;\r
- u8Byte RXByteCnt_B;\r
- u1Byte TrafficLoad;\r
- u1Byte Train_time;\r
- u1Byte Train_time_flag;\r
- RT_TIMER SwAntennaSwitchTimer;\r
-#if (RTL8723B_SUPPORT == 1)||(RTL8821A_SUPPORT == 1) \r
- RT_TIMER SwAntennaSwitchTimer_8723B;\r
- u4Byte PktCnt_SWAntDivByCtrlFrame;\r
- BOOLEAN bSWAntDivByCtrlFrame;\r
-#endif\r
- \r
-#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) \r
- #if USE_WORKITEM\r
- RT_WORK_ITEM SwAntennaSwitchWorkitem;\r
-#if (RTL8723B_SUPPORT == 1)||(RTL8821A_SUPPORT == 1) \r
- RT_WORK_ITEM SwAntennaSwitchWorkitem_8723B;\r
- #endif\r
-#endif\r
-#endif\r
-/* CE Platform use\r
-#ifdef CONFIG_SW_ANTENNA_DIVERSITY\r
- _timer SwAntennaSwitchTimer; \r
- u8Byte lastTxOkCnt;\r
- u8Byte lastRxOkCnt;\r
- u8Byte TXByteCnt_A;\r
- u8Byte TXByteCnt_B;\r
- u8Byte RXByteCnt_A;\r
- u8Byte RXByteCnt_B;\r
- u1Byte DoubleComfirm;\r
- u1Byte TrafficLoad;\r
- //SW Antenna Switch\r
-\r
-\r
-#endif\r
-*/\r
-#ifdef CONFIG_HW_ANTENNA_DIVERSITY\r
- //Hybrid Antenna Diversity\r
- u4Byte CCK_Ant1_Cnt[ASSOCIATE_ENTRY_NUM+1];\r
- u4Byte CCK_Ant2_Cnt[ASSOCIATE_ENTRY_NUM+1];\r
- u4Byte OFDM_Ant1_Cnt[ASSOCIATE_ENTRY_NUM+1];\r
- u4Byte OFDM_Ant2_Cnt[ASSOCIATE_ENTRY_NUM+1];\r
- u4Byte RSSI_Ant1_Sum[ASSOCIATE_ENTRY_NUM+1];\r
- u4Byte RSSI_Ant2_Sum[ASSOCIATE_ENTRY_NUM+1];\r
- u1Byte TxAnt[ASSOCIATE_ENTRY_NUM+1];\r
- u1Byte TargetSTA;\r
- u1Byte antsel;\r
- u1Byte RxIdleAnt;\r
-\r
-#endif\r
- \r
-}SWAT_T, *pSWAT_T;\r
-//#endif\r
-\r
-// Edca Remove by YuChen\r
-\r
-//ODM_RATE_ADAPTIVE Remove by RS_James\r
-\r
-\r
-#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))\r
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
\r
\r
#ifdef ADSL_AP_BUILD_WORKAROUND\r
#define MAX_TOLERANCE 5\r
#define IQK_DELAY_TIME 1 //ms\r
#endif\r
-\r
+#if 0//defined in 8192cd.h\r
//\r
// Indicate different AP vendor for IOT issue.\r
//\r
HT_IOT_PEER_REALTEK_WOW = 15, \r
HT_IOT_PEER_MAX = 16\r
}HT_IOT_PEER_E, *PHTIOT_PEER_E;\r
+#endif\r
#endif//#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))\r
\r
#define DM_Type_ByFW 0\r
//\r
// Declare for common info\r
//\r
-#define MAX_PATH_NUM_92CS 2\r
-#define MAX_PATH_NUM_8188E 1\r
-#define MAX_PATH_NUM_8192E 2\r
-#define MAX_PATH_NUM_8723B 1\r
-#define MAX_PATH_NUM_8812A 2\r
-#define MAX_PATH_NUM_8821A 1\r
-#define MAX_PATH_NUM_8814A 4\r
-#define MAX_PATH_NUM_8822B 2\r
-\r
\r
#define IQK_THRESHOLD 8\r
#define DPK_THRESHOLD 4\r
\r
+\r
+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))\r
+__PACK typedef struct _ODM_Phy_Status_Info_\r
+{\r
+ u1Byte RxPWDBAll; \r
+ u1Byte SignalQuality; // in 0-100 index. \r
+ u1Byte RxMIMOSignalStrength[4];// in 0~100 index\r
+ s1Byte RxMIMOSignalQuality[4]; //EVM\r
+ u1Byte RxSNR[4];//per-path's SNR \r
+ u1Byte BandWidth;\r
+\r
+} __WLAN_ATTRIB_PACK__ ODM_PHY_INFO_T, *PODM_PHY_INFO_T;\r
+\r
+typedef struct _ODM_Phy_Status_Info_Append_\r
+{\r
+ u1Byte MAC_CRC32; \r
+\r
+}ODM_PHY_INFO_Append_T,*PODM_PHY_INFO_Append_T;\r
+\r
+#else\r
+\r
typedef struct _ODM_Phy_Status_Info_\r
{\r
//\r
#else\r
u1Byte RxPWDBAll; \r
#endif\r
-\r
u1Byte SignalQuality; // in 0-100 index. \r
s1Byte RxMIMOSignalQuality[4]; //per-path's EVM\r
u1Byte RxMIMOEVMdbm[4]; //per-path's EVM dbm\r
u1Byte BandWidth;\r
u1Byte btCoexPwrAdjust;\r
}ODM_PHY_INFO_T,*PODM_PHY_INFO_T;\r
-\r
+#endif\r
\r
typedef struct _ODM_Per_Pkt_Info_\r
{\r
\r
}ODM_MAC_INFO;\r
\r
-\r
-typedef enum tag_Dynamic_ODM_Support_Ability_Type\r
-{\r
- // BB Team\r
- ODM_DIG = 0x00000001,\r
- ODM_HIGH_POWER = 0x00000002,\r
- ODM_CCK_CCA_TH = 0x00000004,\r
- ODM_FA_STATISTICS = 0x00000008,\r
- ODM_RAMASK = 0x00000010,\r
- ODM_RSSI_MONITOR = 0x00000020,\r
- ODM_SW_ANTDIV = 0x00000040,\r
- ODM_HW_ANTDIV = 0x00000080,\r
- ODM_BB_PWRSV = 0x00000100,\r
- ODM_2TPATHDIV = 0x00000200,\r
- ODM_1TPATHDIV = 0x00000400,\r
- ODM_PSD2AFH = 0x00000800\r
-}ODM_Ability_E;\r
-\r
//\r
// 2011/20/20 MH For MP driver RT_WLAN_STA = STA_INFO_T\r
// Please declare below ODM relative info in your STA info structure.\r
//1 For 88E RA (don't redefine the naming)\r
u1Byte rate_id;\r
u1Byte rate_SGI;\r
- u1Byte rssi_sta_ra;\v\r
-\r
+ u1Byte rssi_sta_ra;\r
u1Byte SGI_enable;\r
u1Byte Decision_rate;\r
u1Byte Pre_rate;\r
ODM_CMNINFO_GLNA,\r
ODM_CMNINFO_ALNA,\r
ODM_CMNINFO_EXT_TRSW,\r
+ ODM_CMNINFO_EXT_LNA_GAIN,\r
ODM_CMNINFO_PATCH_ID, //CUSTOMER ID\r
ODM_CMNINFO_BINHCT_TEST,\r
ODM_CMNINFO_BWIFI_TEST,\r
ODM_CMNINFO_SMART_CONCURRENT,\r
+ ODM_CMNINFO_CONFIG_BB_RF,\r
ODM_CMNINFO_DOMAIN_CODE_2G,\r
ODM_CMNINFO_DOMAIN_CODE_5G,\r
ODM_CMNINFO_IQKFWOFFLOAD,\r
ODM_CMNINFO_BT_HS_RSSI,\r
ODM_CMNINFO_BT_OPERATION,\r
ODM_CMNINFO_BT_LIMITED_DIG, //Need to Limited Dig or not\r
+ ODM_CMNINFO_BT_DIG,\r
+ ODM_CMNINFO_BT_BUSY, //Check Bt is using or not//neil \r
ODM_CMNINFO_BT_DISABLE_EDCA,\r
-#if(DM_ODM_SUPPORT_TYPE & ODM_AP) // for repeater mode add by YuChen 2014.06.\r
+#if(DM_ODM_SUPPORT_TYPE & ODM_AP) // for repeater mode add by YuChen 2014.06.23\r
#ifdef UNIVERSAL_REPEATER\r
ODM_CMNINFO_VXD_LINK,\r
#endif\r
#endif\r
- \r
+ ODM_CMNINFO_AP_TOTAL_NUM,\r
//------------CALL BY VALUE-------------//\r
\r
//\r
ODM_BB_DYNAMIC_TXPWR = BIT2,\r
ODM_BB_FA_CNT = BIT3,\r
ODM_BB_RSSI_MONITOR = BIT4,\r
- ODM_BB_CCK_PD = BIT5,\r
+ ODM_BB_CCK_PD = BIT5,\r
ODM_BB_ANT_DIV = BIT6,\r
ODM_BB_PWR_SAVE = BIT7,\r
ODM_BB_PWR_TRAIN = BIT8,\r
ODM_BB_CFO_TRACKING = BIT14,\r
ODM_BB_NHM_CNT = BIT15,\r
ODM_BB_PRIMARY_CCA = BIT16,\r
+ ODM_BB_TXBF = BIT17,\r
\r
//\r
// MAC DM section BIT 20-23\r
//\r
ODM_RF_TX_PWR_TRACK = BIT24,\r
ODM_RF_RX_GAIN_TRACK = BIT25,\r
- ODM_RF_CALIBRATION = BIT26,\r
+ ODM_RF_CALIBRATION = BIT26,\r
\r
}ODM_ABILITY_E;\r
\r
-// ODM_CMNINFO_INTERFACE\r
-typedef enum tag_ODM_Support_Interface_Definition\r
-{\r
- ODM_ITRF_PCIE = 0x1,\r
- ODM_ITRF_USB = 0x2,\r
- ODM_ITRF_SDIO = 0x4,\r
- ODM_ITRF_ALL = 0x7,\r
-}ODM_INTERFACE_E;\r
-\r
-// ODM_CMNINFO_IC_TYPE\r
-typedef enum tag_ODM_Support_IC_Type_Definition\r
-{\r
- ODM_RTL8192S = BIT0,\r
- ODM_RTL8192C = BIT1,\r
- ODM_RTL8192D = BIT2,\r
- ODM_RTL8723A = BIT3,\r
- ODM_RTL8188E = BIT4,\r
- ODM_RTL8812 = BIT5,\r
- ODM_RTL8821 = BIT6,\r
- ODM_RTL8192E = BIT7, \r
- ODM_RTL8723B = BIT8,\r
- ODM_RTL8814A = BIT9, \r
- ODM_RTL8881A = BIT10,\r
- ODM_RTL8821B = BIT11,\r
- ODM_RTL8822B = BIT12,\r
- ODM_RTL8703B = BIT13\r
-}ODM_IC_TYPE_E;\r
-\r
-#define ODM_IC_11N_SERIES (ODM_RTL8192S|ODM_RTL8192C|ODM_RTL8192D|ODM_RTL8723A|ODM_RTL8188E|ODM_RTL8192E|ODM_RTL8723B|ODM_RTL8703B)\r
-#define ODM_IC_11AC_SERIES (ODM_RTL8812|ODM_RTL8821|ODM_RTL8814A|ODM_RTL8881A|ODM_RTL8821B|ODM_RTL8822B)\r
-\r
-#if (DM_ODM_SUPPORT_TYPE == ODM_AP)\r
-\r
-#ifdef RTK_AC_SUPPORT\r
-#define ODM_IC_11AC_SERIES_SUPPORT 1\r
-#else\r
-#define ODM_IC_11AC_SERIES_SUPPORT 0\r
-#endif\r
-\r
-#define ODM_IC_11N_SERIES_SUPPORT 1\r
-#define ODM_CONFIG_BT_COEXIST 0\r
-\r
-#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
-\r
-#define ODM_IC_11AC_SERIES_SUPPORT 1\r
-#define ODM_IC_11N_SERIES_SUPPORT 1\r
-#define ODM_CONFIG_BT_COEXIST 1\r
-\r
-#else \r
-\r
-#if((RTL8192C_SUPPORT == 1) || (RTL8192D_SUPPORT == 1) || (RTL8723A_SUPPORT == 1) || (RTL8188E_SUPPORT == 1) ||\\r
-(RTL8723B_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8195A_SUPPORT == 1))\r
-#define ODM_IC_11N_SERIES_SUPPORT 1\r
-#define ODM_IC_11AC_SERIES_SUPPORT 0\r
-#else\r
-#define ODM_IC_11N_SERIES_SUPPORT 0\r
-#define ODM_IC_11AC_SERIES_SUPPORT 1\r
-#endif\r
-\r
-#ifdef CONFIG_BT_COEXIST\r
-#define ODM_CONFIG_BT_COEXIST 1\r
-#else\r
-#define ODM_CONFIG_BT_COEXIST 0\r
-#endif\r
-\r
-#endif\r
-\r
-\r
-//ODM_CMNINFO_CUT_VER\r
-typedef enum tag_ODM_Cut_Version_Definition\r
-{\r
- ODM_CUT_A = 0,\r
- ODM_CUT_B = 1,\r
- ODM_CUT_C = 2,\r
- ODM_CUT_D = 3,\r
- ODM_CUT_E = 4,\r
- ODM_CUT_F = 5,\r
-\r
- ODM_CUT_I = 8,\r
- ODM_CUT_J = 9,\r
- ODM_CUT_K = 10, \r
- ODM_CUT_TEST = 15,\r
-}ODM_CUT_VERSION_E;\r
-\r
-// ODM_CMNINFO_FAB_VER\r
-typedef enum tag_ODM_Fab_Version_Definition\r
-{\r
- ODM_TSMC = 0,\r
- ODM_UMC = 1,\r
-}ODM_FAB_E;\r
-\r
-// ODM_CMNINFO_RF_TYPE\r
-//\r
-// For example 1T2R (A+AB = BIT0|BIT4|BIT5)\r
-//\r
-typedef enum tag_ODM_RF_Path_Bit_Definition\r
-{\r
- ODM_RF_TX_A = BIT0,\r
- ODM_RF_TX_B = BIT1,\r
- ODM_RF_TX_C = BIT2,\r
- ODM_RF_TX_D = BIT3,\r
- ODM_RF_RX_A = BIT4,\r
- ODM_RF_RX_B = BIT5,\r
- ODM_RF_RX_C = BIT6,\r
- ODM_RF_RX_D = BIT7,\r
-}ODM_RF_PATH_E;\r
-\r
-\r
-typedef enum tag_ODM_RF_Type_Definition\r
-{\r
- ODM_1T1R = 0,\r
- ODM_1T2R = 1,\r
- ODM_2T2R = 2,\r
- ODM_2T3R = 3,\r
- ODM_2T4R = 4,\r
- ODM_3T3R = 5,\r
- ODM_3T4R = 6,\r
- ODM_4T4R = 7,\r
-}ODM_RF_TYPE_E;\r
-\r
-\r
-//\r
-// ODM Dynamic common info value definition\r
-//\r
-\r
-//typedef enum _MACPHY_MODE_8192D{\r
-// SINGLEMAC_SINGLEPHY,\r
-// DUALMAC_DUALPHY,\r
-// DUALMAC_SINGLEPHY,\r
-//}MACPHY_MODE_8192D,*PMACPHY_MODE_8192D;\r
-// Above is the original define in MP driver. Please use the same define. THX.\r
-typedef enum tag_ODM_MAC_PHY_Mode_Definition\r
-{\r
- ODM_SMSP = 0,\r
- ODM_DMSP = 1,\r
- ODM_DMDP = 2,\r
-}ODM_MAC_PHY_MODE_E;\r
-\r
-\r
-typedef enum tag_BT_Coexist_Definition\r
-{ \r
- ODM_BT_BUSY = 1,\r
- ODM_BT_ON = 2,\r
- ODM_BT_OFF = 3,\r
- ODM_BT_NONE = 4,\r
-}ODM_BT_COEXIST_E;\r
-\r
-// ODM_CMNINFO_OP_MODE\r
-typedef enum tag_Operation_Mode_Definition\r
-{\r
- ODM_NO_LINK = BIT0,\r
- ODM_LINK = BIT1,\r
- ODM_SCAN = BIT2,\r
- ODM_POWERSAVE = BIT3,\r
- ODM_AP_MODE = BIT4,\r
- ODM_CLIENT_MODE = BIT5,\r
- ODM_AD_HOC = BIT6,\r
- ODM_WIFI_DIRECT = BIT7,\r
- ODM_WIFI_DISPLAY = BIT8,\r
-}ODM_OPERATION_MODE_E;\r
-\r
-// ODM_CMNINFO_WM_MODE\r
-#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_CE))\r
-typedef enum tag_Wireless_Mode_Definition\r
-{\r
- ODM_WM_UNKNOW = 0x0,\r
- ODM_WM_B = BIT0,\r
- ODM_WM_G = BIT1,\r
- ODM_WM_A = BIT2,\r
- ODM_WM_N24G = BIT3,\r
- ODM_WM_N5G = BIT4,\r
- ODM_WM_AUTO = BIT5,\r
- ODM_WM_AC = BIT6,\r
-}ODM_WIRELESS_MODE_E;\r
-#else\r
-typedef enum tag_Wireless_Mode_Definition\r
-{\r
- ODM_WM_UNKNOWN = 0x00,\r
- ODM_WM_A = BIT0,\r
- ODM_WM_B = BIT1,\r
- ODM_WM_G = BIT2,\r
- ODM_WM_AUTO = BIT3,\r
- ODM_WM_N24G = BIT4,\r
- ODM_WM_N5G = BIT5,\r
- ODM_WM_AC_5G = BIT6,\r
- ODM_WM_AC_24G = BIT7,\r
- ODM_WM_AC_ONLY = BIT8,\r
- ODM_WM_MAX = BIT9\r
-}ODM_WIRELESS_MODE_E;\r
-#endif\r
-\r
-// ODM_CMNINFO_BAND\r
-typedef enum tag_Band_Type_Definition\r
-{\r
- ODM_BAND_2_4G = 0,\r
- ODM_BAND_5G,\r
- ODM_BAND_ON_BOTH,\r
- ODM_BANDMAX\r
-\r
-}ODM_BAND_TYPE_E;\r
-\r
-// ODM_CMNINFO_SEC_CHNL_OFFSET\r
-typedef enum tag_Secondary_Channel_Offset_Definition\r
-{\r
- ODM_DONT_CARE = 0,\r
- ODM_BELOW = 1,\r
- ODM_ABOVE = 2\r
-}ODM_SEC_CHNL_OFFSET_E;\r
-\r
-// ODM_CMNINFO_SEC_MODE\r
-typedef enum tag_Security_Definition\r
-{\r
- ODM_SEC_OPEN = 0,\r
- ODM_SEC_WEP40 = 1,\r
- ODM_SEC_TKIP = 2,\r
- ODM_SEC_RESERVE = 3,\r
- ODM_SEC_AESCCMP = 4,\r
- ODM_SEC_WEP104 = 5,\r
- ODM_WEP_WPA_MIXED = 6, // WEP + WPA\r
- ODM_SEC_SMS4 = 7,\r
-}ODM_SECURITY_E;\r
-\r
-// ODM_CMNINFO_BW\r
-typedef enum tag_Bandwidth_Definition\r
-{ \r
- ODM_BW20M = 0,\r
- ODM_BW40M = 1,\r
- ODM_BW80M = 2,\r
- ODM_BW160M = 3,\r
- ODM_BW10M = 4,\r
-}ODM_BW_E;\r
-\r
-\r
-// ODM_CMNINFO_BOARD_TYPE\r
-// For non-AC-series IC , ODM_BOARD_5G_EXT_PA and ODM_BOARD_5G_EXT_LNA are ignored\r
-// For AC-series IC, external PA & LNA can be indivisuallly added on 2.4G and/or 5G \r
-typedef enum tag_Board_Definition\r
-{\r
- ODM_BOARD_DEFAULT = 0, // The DEFAULT case.\r
- ODM_BOARD_MINICARD = BIT(0), // 0 = non-mini card, 1= mini card.\r
- ODM_BOARD_SLIM = BIT(1), // 0 = non-slim card, 1 = slim card\r
- ODM_BOARD_BT = BIT(2), // 0 = without BT card, 1 = with BT\r
- ODM_BOARD_EXT_PA = BIT(3), // 0 = no 2G ext-PA, 1 = existing 2G ext-PA\r
- ODM_BOARD_EXT_LNA = BIT(4), // 0 = no 2G ext-LNA, 1 = existing 2G ext-LNA\r
- ODM_BOARD_EXT_TRSW = BIT(5), // 0 = no ext-TRSW, 1 = existing ext-TRSW\r
- ODM_BOARD_EXT_PA_5G = BIT(6), // 0 = no 5G ext-PA, 1 = existing 5G ext-PA\r
- ODM_BOARD_EXT_LNA_5G= BIT(7), // 0 = no 5G ext-LNA, 1 = existing 5G ext-LNA\r
-}ODM_BOARD_TYPE_E;\r
-\r
-typedef enum tag_ODM_Package_Definition\r
-{\r
- ODM_PACKAGE_DEFAULT = 0, \r
- ODM_PACKAGE_QFN68 = BIT(0), \r
- ODM_PACKAGE_TFBGA90 = BIT(1), \r
- ODM_PACKAGE_TFBGA79 = BIT(2), \r
-}ODM_Package_TYPE_E;\r
-\r
-typedef enum tag_ODM_TYPE_GPA_Definition\r
-{\r
- TYPE_GPA0 = 0, \r
- TYPE_GPA1 = BIT(1)|BIT(0)\r
-}ODM_TYPE_GPA_E;\r
-\r
-typedef enum tag_ODM_TYPE_APA_Definition\r
-{\r
- TYPE_APA0 = 0, \r
- TYPE_APA1 = BIT(1)|BIT(0)\r
-}ODM_TYPE_APA_E;\r
-\r
-typedef enum tag_ODM_TYPE_GLNA_Definition\r
-{\r
- TYPE_GLNA0 = 0, \r
- TYPE_GLNA1 = BIT(2)|BIT(0),\r
- TYPE_GLNA2 = BIT(3)|BIT(1),\r
- TYPE_GLNA3 = BIT(3)|BIT(2)|BIT(1)|BIT(0)\r
-}ODM_TYPE_GLNA_E;\r
-\r
-typedef enum tag_ODM_TYPE_ALNA_Definition\r
-{\r
- TYPE_ALNA0 = 0, \r
- TYPE_ALNA1 = BIT(2)|BIT(0),\r
- TYPE_ALNA2 = BIT(3)|BIT(1),\r
- TYPE_ALNA3 = BIT(3)|BIT(2)|BIT(1)|BIT(0)\r
-}ODM_TYPE_ALNA_E;\r
+//Move some non-DM enum,define, struc. form phydm.h to phydm_types.h by Dino\r
\r
// ODM_CMNINFO_ONE_PATH_CCA\r
typedef enum tag_CCA_Path\r
ODM_CCA_1R_B = 2,\r
}ODM_CCA_PATH_E;\r
\r
-\r
-typedef struct _ODM_RA_Info_\r
-{\r
- u1Byte RateID;\r
- u4Byte RateMask;\r
- u4Byte RAUseRate;\r
- u1Byte RateSGI;\r
- u1Byte RssiStaRA;\r
- u1Byte PreRssiStaRA;\r
- u1Byte SGIEnable;\r
- u1Byte DecisionRate;\r
- u1Byte PreRate;\r
- u1Byte HighestRate;\r
- u1Byte LowestRate;\r
- u4Byte NscUp;\r
- u4Byte NscDown;\r
- u2Byte RTY[5];\r
- u4Byte TOTAL;\r
- u2Byte DROP;\r
- u1Byte Active;\r
- u2Byte RptTime;\r
- u1Byte RAWaitingCounter;\r
- u1Byte RAPendingCounter; \r
-#if 1 //POWER_TRAINING_ACTIVE == 1 // For compile pass only~!\r
- u1Byte PTActive; // on or off\r
- u1Byte PTTryState; // 0 trying state, 1 for decision state\r
- u1Byte PTStage; // 0~6\r
- u1Byte PTStopCount; //Stop PT counter\r
- u1Byte PTPreRate; // if rate change do PT\r
- u1Byte PTPreRssi; // if RSSI change 5% do PT\r
- u1Byte PTModeSS; // decide whitch rate should do PT\r
- u1Byte RAstage; // StageRA, decide how many times RA will be done between PT\r
- u1Byte PTSmoothFactor;\r
-#endif\r
-} ODM_RA_INFO_T,*PODM_RA_INFO_T;\r
+//move RAInfo to Phydm_RaInfo.h\r
\r
//Remove struct PATHDIV_PARA to odm_PathDiv.h \r
\r
-//move to PowerTracking.h by YuChen\r
-\r
+//Remove struct to odm_PowerTracking.h by YuChen\r
//\r
// ODM Dynamic common info value definition\r
//\r
+//Move AntDiv form phydm.h to Phydm_AntDiv.h by Dino\r
\r
-typedef struct _FAST_ANTENNA_TRAINNING_\r
-{\r
- u1Byte Bssid[6];\r
- u1Byte antsel_rx_keep_0;\r
- u1Byte antsel_rx_keep_1;\r
- u1Byte antsel_rx_keep_2;\r
- u1Byte antsel_rx_keep_3;\r
- u4Byte antSumRSSI[7];\r
- u4Byte antRSSIcnt[7];\r
- u4Byte antAveRSSI[7];\r
- u1Byte FAT_State;\r
- u4Byte TrainIdx;\r
- u1Byte antsel_a[ODM_ASSOCIATE_ENTRY_NUM];\r
- u1Byte antsel_b[ODM_ASSOCIATE_ENTRY_NUM];\r
- u1Byte antsel_c[ODM_ASSOCIATE_ENTRY_NUM];\r
- u4Byte MainAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM];\r
- u4Byte AuxAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM];\r
- u4Byte MainAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM];\r
- u4Byte AuxAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM];\r
- u1Byte RxIdleAnt;\r
- BOOLEAN bBecomeLinked;\r
- u4Byte MinMaxRSSI;\r
- u1Byte idx_AntDiv_counter_2G;\r
- u1Byte idx_AntDiv_counter_5G;\r
- u4Byte AntDiv_2G_5G;\r
- u4Byte CCK_counter_main;\r
- u4Byte CCK_counter_aux; \r
- u4Byte OFDM_counter_main;\r
- u4Byte OFDM_counter_aux; \r
-\r
-\r
- u4Byte CCK_CtrlFrame_Cnt_main;\r
- u4Byte CCK_CtrlFrame_Cnt_aux;\r
- u4Byte OFDM_CtrlFrame_Cnt_main;\r
- u4Byte OFDM_CtrlFrame_Cnt_aux;\r
- u4Byte MainAnt_CtrlFrame_Sum;\r
- u4Byte AuxAnt_CtrlFrame_Sum;\r
- u4Byte MainAnt_CtrlFrame_Cnt;\r
- u4Byte AuxAnt_CtrlFrame_Cnt;\r
-\r
-}FAT_T,*pFAT_T;\r
-\r
-typedef enum _FAT_STATE\r
-{\r
- FAT_NORMAL_STATE = 0,\r
- FAT_TRAINING_STATE = 1,\r
-}FAT_STATE_E, *PFAT_STATE_E;\r
-\r
-typedef enum _ANT_DIV_TYPE\r
-{\r
- NO_ANTDIV = 0xFF, \r
- CG_TRX_HW_ANTDIV = 0x01,\r
- CGCS_RX_HW_ANTDIV = 0x02,\r
- FIXED_HW_ANTDIV = 0x03,\r
- CG_TRX_SMART_ANTDIV = 0x04,\r
- CGCS_RX_SW_ANTDIV = 0x05,\r
- S0S1_SW_ANTDIV = 0x06 //8723B intrnal switch S0 S1\r
-}ANT_DIV_TYPE_E, *PANT_DIV_TYPE_E;\r
-\r
-\r
-typedef struct _ODM_PATH_DIVERSITY_\r
-{\r
- u1Byte RespTxPath;\r
- u1Byte PathSel[ODM_ASSOCIATE_ENTRY_NUM];\r
- u4Byte PathA_Sum[ODM_ASSOCIATE_ENTRY_NUM];\r
- u4Byte PathB_Sum[ODM_ASSOCIATE_ENTRY_NUM];\r
- u4Byte PathA_Cnt[ODM_ASSOCIATE_ENTRY_NUM];\r
- u4Byte PathB_Cnt[ODM_ASSOCIATE_ENTRY_NUM];\r
-}PATHDIV_T, *pPATHDIV_T;\r
-\r
+//move PathDiv to Phydm_PathDiv.h\r
\r
typedef enum _BASEBAND_CONFIG_PHY_REG_PG_VALUE_TYPE{\r
PHY_REG_PG_RELATIVE_VALUE = 0,\r
PHY_REG_PG_EXACT_VALUE = 1\r
} PHY_REG_PG_TYPE;\r
\r
-\r
-//\r
-// Antenna detection information from single tone mechanism, added by Roger, 2012.11.27.\r
-//\r
-typedef struct _ANT_DETECTED_INFO{\r
- BOOLEAN bAntDetected;\r
- u4Byte dBForAntA;\r
- u4Byte dBForAntB;\r
- u4Byte dBForAntO;\r
-}ANT_DETECTED_INFO, *PANT_DETECTED_INFO;\r
-\r
//\r
// 2011/09/22 MH Copy from SD4 defined structure. We use to support PHY DM integration.\r
//\r
#if (RT_PLATFORM != PLATFORM_LINUX)\r
typedef \r
#endif\r
+ \r
struct DM_Out_Source_Dynamic_Mechanism_Structure\r
#else// for AP,ADSL,CE Team\r
typedef struct DM_Out_Source_Dynamic_Mechanism_Structure\r
u1Byte TypeALNA;\r
u1Byte TypeAPA;\r
// with external LNA NO/Yes = 0/1\r
- u1Byte ExtLNA;\r
- u1Byte ExtLNA5G;\r
+ u1Byte ExtLNA; // 2G\r
+ u1Byte ExtLNA5G; //5G\r
// with external PA NO/Yes = 0/1\r
- u1Byte ExtPA;\r
- u1Byte ExtPA5G;\r
+ u1Byte ExtPA; // 2G\r
+ u1Byte ExtPA5G; //5G\r
// with external TRSW NO/Yes = 0/1\r
u1Byte ExtTRSW;\r
+ u1Byte ExtLNAGain; // 2G\r
u1Byte PatchID; //Customer ID\r
BOOLEAN bInHctTest;\r
BOOLEAN bWIFITest;\r
BOOLEAN bDualMacSmartConcurrent;\r
u4Byte BK_SupportAbility;\r
u1Byte AntDivType;\r
-\r
+ BOOLEAN ConfigBBRF;\r
u1Byte odm_Regulation2_4G;\r
u1Byte odm_Regulation5G;\r
u1Byte IQKFWOffload;\r
//u1Byte *pAidMap;\r
u1Byte *pu1ForcedIgiLb;\r
BOOLEAN *pIsFcsModeEnable;\r
-//--------- For 8723B IQK-----------//\r
+/*--------- For 8723B IQK-----------*/\r
BOOLEAN *pIs1Antenna;\r
u1Byte *pRFDefaultPath;\r
// 0:S1, 1:S0\r
BOOLEAN bWIFI_Display;\r
BOOLEAN bLinked;\r
BOOLEAN bsta_state;\r
+#if(DM_ODM_SUPPORT_TYPE & ODM_AP) // for repeater mode add by YuChen 2014.06.23\r
+#ifdef UNIVERSAL_REPEATER\r
+ BOOLEAN VXD_bLinked;\r
+#endif\r
+#endif // for repeater mode add by YuChen 2014.06.23 \r
u1Byte RSSI_Min; \r
- u1Byte InterfaceIndex; // Add for 92D dual MAC: 0--Mac0 1--Mac1\r
- BOOLEAN bIsMPChip;\r
+ u1Byte InterfaceIndex; /*Add for 92D dual MAC: 0--Mac0 1--Mac1*/\r
+ BOOLEAN bIsMPChip;\r
BOOLEAN bOneEntryOnly;\r
BOOLEAN mp_mode;\r
+ u4Byte OneEntry_MACID;\r
+ u1Byte pre_number_linked_client; \r
+ u1Byte number_linked_client;\r
+ u1Byte pre_number_active_client; \r
+ u1Byte number_active_client;\r
// Common info for BTDM\r
BOOLEAN bBtEnabled; // BT is enabled\r
BOOLEAN bBtConnectProcess; // BT HS is under connection progress.\r
u1Byte btHsRssi; // BT HS mode wifi rssi value.\r
BOOLEAN bBtHsOperation; // BT HS mode is under progress\r
+ u1Byte btHsDigVal; // use BT rssi to decide the DIG value\r
BOOLEAN bBtDisableEdcaTurbo; // Under some condition, don't enable the EDCA Turbo\r
+ BOOLEAN bBtBusy; // BT is busy.\r
BOOLEAN bBtLimitedDig; // BT is busy.\r
//------------CALL BY VALUE-------------//\r
u1Byte RSSI_A;\r
u8Byte RSSI_TRSW_H;\r
u8Byte RSSI_TRSW_L; \r
u8Byte RSSI_TRSW_iso;\r
+ u1Byte TRXAntStatus;\r
\r
u1Byte RxRate;\r
BOOLEAN bNoisyState;\r
BOOLEAN IsBbSwingOffsetPositiveA;\r
u4Byte BbSwingOffsetB;\r
BOOLEAN IsBbSwingOffsetPositiveB;\r
- s1Byte TH_L2H_ini;\r
- s1Byte TH_EDCCA_HL_diff;\r
- s1Byte IGI_Base;\r
- u1Byte IGI_target;\r
- BOOLEAN ForceEDCCA;\r
- u1Byte AdapEn_RSSI;\r
- s1Byte Force_TH_H;\r
- s1Byte Force_TH_L;\r
- u1Byte IGI_LowerBound;\r
- u1Byte antdiv_rssi;\r
+ u1Byte antdiv_rssi;\r
+ u1Byte fat_comb_a;\r
+ u1Byte fat_comb_b;\r
+ u1Byte antdiv_intvl;\r
u1Byte AntType;\r
u1Byte pre_AntType;\r
- u1Byte antdiv_period;\r
- u1Byte antdiv_select; \r
+ u1Byte antdiv_period;\r
+ u1Byte antdiv_select;\r
+ u1Byte path_select; \r
+ u1Byte antdiv_evm_en;\r
+ u1Byte bdc_holdstate;\r
u1Byte NdpaPeriod;\r
BOOLEAN H2C_RARpt_connect;\r
+ BOOLEAN cck_agc_report_type;\r
+ \r
+ u1Byte dm_dig_max_TH;\r
+ u1Byte dm_dig_min_TH;\r
+ u1Byte print_agc;\r
\r
- // add by Yu Cehn for adaptivtiy\r
- BOOLEAN adaptivity_flag;\r
- u1Byte tolerance_cnt;\r
- u8Byte NHMCurTxOkcnt;\r
- u8Byte NHMCurRxOkcnt;\r
- u8Byte NHMLastTxOkcnt;\r
- u8Byte NHMLastRxOkcnt;\r
- u1Byte NHMWait;\r
- s1Byte H2L_lb;\r
- s1Byte L2H_lb;\r
- u1Byte Adaptivity_IGI_upper;\r
+ //For Adaptivtiy\r
u2Byte NHM_cnt_0;\r
u2Byte NHM_cnt_1;\r
+ s1Byte TH_L2H_ini;\r
+ s1Byte TH_EDCCA_HL_diff;\r
+ s1Byte TH_L2H_ini_backup;\r
BOOLEAN Carrier_Sense_enable;\r
- BOOLEAN bFirstLink;\r
- BOOLEAN bCheck;\r
- BOOLEAN EDCCA_enable_state;\r
- BOOLEAN NHM_enable;\r
- BOOLEAN DynamicLinkAdaptivity;\r
- BOOLEAN bAdaOn;\r
+ u1Byte Adaptivity_IGI_upper;\r
+ BOOLEAN adaptivity_flag;\r
+ u1Byte DCbackoff;\r
+ BOOLEAN Adaptivity_enable;\r
+ u1Byte APTotalNum;\r
+ ADAPTIVITY_STATISTICS Adaptivity;\r
+ //For Adaptivtiy\r
+ u1Byte LastUSBHub;\r
+ \r
+ u1Byte c2h_cmd_start;\r
+ u1Byte fw_debug_trace[60]; \r
+ u1Byte pre_c2h_seq;\r
+ BOOLEAN fw_buff_is_enpty;\r
\r
+#if (DM_ODM_SUPPORT_TYPE & (ODM_CE))\r
ODM_NOISE_MONITOR noise_level;//[ODM_MAX_CHANNEL_NUM];\r
+#endif\r
//\r
//2 Define STA info.\r
// _ODM_STA_INFO\r
// 2012/01/12 MH For MP, we need to reduce one array pointer for default port.??\r
PSTA_INFO_T pODM_StaInfo[ODM_ASSOCIATE_ENTRY_NUM];\r
+ u2Byte platform2phydm_macid_table[ODM_ASSOCIATE_ENTRY_NUM]; /* platform_macid_table[platform_macid] = phydm_macid */\r
\r
#if (RATE_ADAPTIVE_SUPPORT == 1)\r
u2Byte CurrminRptTime;\r
- ODM_RA_INFO_T RAInfo[ODM_ASSOCIATE_ENTRY_NUM]; //See HalMacID support\r
+ ODM_RA_INFO_T RAInfo[ODM_ASSOCIATE_ENTRY_NUM]; //Use MacID as array index. STA MacID=0, VWiFi Client MacID={1, ODM_ASSOCIATE_ENTRY_NUM-1} //YJ,add,120119\r
#endif\r
//\r
// 2012/02/14 MH Add to share 88E ra with other SW team.\r
//\r
//ODM Structure\r
//\r
+ #if (defined(CONFIG_HW_ANTENNA_DIVERSITY))\r
+ #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))\r
+ BDC_T DM_BdcTable;\r
+ #endif\r
+ #endif\r
FAT_T DM_FatTable;\r
DIG_T DM_DigTable;\r
PS_T DM_PSTable;\r
RA_T DM_RA_Table; \r
FALSE_ALARM_STATISTICS FalseAlmCnt;\r
FALSE_ALARM_STATISTICS FlaseAlmCntBuddyAdapter;\r
- //#ifdef CONFIG_ANTENNA_DIVERSITY\r
SWAT_T DM_SWAT_Table;\r
BOOLEAN RSSI_test;\r
CFO_TRACKING DM_CfoTrack;\r
ACS DM_ACS;\r
- //#endif \r
- \r
+\r
+#if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_AP))\r
+#if (RTL8814A_SUPPORT == 1)\r
+ IQK_INFO IQK_info;\r
+#endif /* (RTL8814A_SUPPORT==1) */\r
+#endif\r
+\r
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)\r
//Path Div Struct\r
PATHDIV_PARA pathIQK;\r
+#endif\r
+#if(defined(CONFIG_PATH_DIVERSITY))\r
+ PATHDIV_T DM_PathDiv;\r
#endif \r
\r
EDCA_T DM_EDCA_Table;\r
u4Byte WMMEDCA_BE;\r
- PATHDIV_T DM_PathDiv;\r
+\r
// Copy from SD4 structure\r
//\r
// ==================================================\r
u1Byte bUseRAMask;\r
\r
ODM_RATE_ADAPTIVE RateAdaptive;\r
-\r
+//#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))\r
+#if(defined(CONFIG_ANT_DETECTION))\r
ANT_DETECTED_INFO AntDetectedInfo; // Antenna detected information for RSSI tool\r
-\r
+#endif\r
ODM_RF_CAL_T RFCalibrateInfo;\r
- \r
- //\r
- // TX power tracking\r
- //\r
- u1Byte BbSwingIdxOfdm[MAX_RF_PATH];\r
- u1Byte BbSwingIdxOfdmCurrent;\r
- u1Byte BbSwingIdxOfdmBase[MAX_RF_PATH];\r
- BOOLEAN BbSwingFlagOfdm;\r
- u1Byte BbSwingIdxCck;\r
- u1Byte BbSwingIdxCckCurrent;\r
- u1Byte BbSwingIdxCckBase;\r
- u1Byte DefaultOfdmIndex;\r
- u1Byte DefaultCckIndex; \r
- BOOLEAN BbSwingFlagCck;\r
- \r
- s1Byte Absolute_OFDMSwingIdx[MAX_RF_PATH]; \r
- s1Byte Remnant_OFDMSwingIdx[MAX_RF_PATH]; \r
- s1Byte Remnant_CCKSwingIdx;\r
- s1Byte Modify_TxAGC_Value; //Remnat compensate value at TxAGC \r
- BOOLEAN Modify_TxAGC_Flag_PathA;\r
- BOOLEAN Modify_TxAGC_Flag_PathB;\r
- BOOLEAN Modify_TxAGC_Flag_PathC;\r
- BOOLEAN Modify_TxAGC_Flag_PathD;\r
- BOOLEAN Modify_TxAGC_Flag_PathA_CCK;\r
- \r
- s1Byte KfreeOffset[MAX_RF_PATH];\r
\r
+ \r
//\r
// Dynamic ATC switch\r
//\r
//2011.09.27 add for Path Diversity\r
RT_TIMER CCKPathDiversityTimer;\r
RT_TIMER FastAntTrainingTimer;\r
- \r
+#ifdef ODM_EVM_ENHANCE_ANTDIV\r
+ RT_TIMER EVM_FastAntTrainingTimer;\r
+#endif\r
+ RT_TIMER sbdcnt_timer;\r
+\r
// ODM relative workitem.\r
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
- #if USE_WORKITEM\r
+#if USE_WORKITEM\r
RT_WORK_ITEM PathDivSwitchWorkitem;\r
RT_WORK_ITEM CCKPathDiversityWorkitem;\r
RT_WORK_ITEM FastAntTrainingWorkitem;\r
RT_WORK_ITEM MPT_DIGWorkitem;\r
RT_WORK_ITEM RaRptWorkitem;\r
- #endif\r
+ RT_WORK_ITEM sbdcnt_workitem;\r
#endif\r
\r
- #if (BEAMFORMING_SUPPORT == 1)\r
+#if (BEAMFORMING_SUPPORT == 1)\r
RT_BEAMFORMING_INFO BeamformingInfo;\r
- #endif \r
+#endif \r
+#endif\r
\r
#if(DM_ODM_SUPPORT_TYPE & ODM_WIN)\r
\r
#endif\r
\r
\r
-\r
-#if 1 //92c-series\r
-#define ODM_RF_PATH_MAX 2\r
-#else //jaguar - series\r
-#define ODM_RF_PATH_MAX 4\r
-#endif\r
-\r
-typedef enum _PhyDM_Structure_Type{\r
+typedef enum _PHYDM_STRUCTURE_TYPE{\r
PHYDM_FALSEALMCNT,\r
PHYDM_CFOTRACK,\r
+ PHYDM_ADAPTIVITY,\r
PHYDM_ROMINFO,\r
\r
-}PhyDM_Structure_Type;\r
-\r
-typedef enum _ODM_RF_RADIO_PATH {\r
- ODM_RF_PATH_A = 0, //Radio Path A\r
- ODM_RF_PATH_B = 1, //Radio Path B\r
- ODM_RF_PATH_C = 2, //Radio Path C\r
- ODM_RF_PATH_D = 3, //Radio Path D\r
- ODM_RF_PATH_AB,\r
- ODM_RF_PATH_AC,\r
- ODM_RF_PATH_AD,\r
- ODM_RF_PATH_BC,\r
- ODM_RF_PATH_BD,\r
- ODM_RF_PATH_CD,\r
- ODM_RF_PATH_ABC,\r
- ODM_RF_PATH_ACD,\r
- ODM_RF_PATH_BCD,\r
- ODM_RF_PATH_ABCD,\r
- // ODM_RF_PATH_MAX, //Max RF number 90 support\r
-} ODM_RF_RADIO_PATH_E, *PODM_RF_RADIO_PATH_E;\r
+}PHYDM_STRUCTURE_TYPE;\r
+\r
+\r
\r
typedef enum _ODM_RF_CONTENT{\r
odm_radioa_txt = 0x1000,\r
} ODM_RF_CONTENT;\r
\r
typedef enum _ODM_BB_Config_Type{\r
- CONFIG_BB_PHY_REG, \r
- CONFIG_BB_AGC_TAB, \r
- CONFIG_BB_AGC_TAB_2G,\r
- CONFIG_BB_AGC_TAB_5G, \r
- CONFIG_BB_PHY_REG_PG, \r
- CONFIG_BB_PHY_REG_MP,\r
- CONFIG_BB_AGC_TAB_DIFF,\r
+ CONFIG_BB_PHY_REG, \r
+ CONFIG_BB_AGC_TAB, \r
+ CONFIG_BB_AGC_TAB_2G,\r
+ CONFIG_BB_AGC_TAB_5G, \r
+ CONFIG_BB_PHY_REG_PG,\r
+ CONFIG_BB_PHY_REG_MP,\r
+ CONFIG_BB_AGC_TAB_DIFF,\r
} ODM_BB_Config_Type, *PODM_BB_Config_Type;\r
\r
typedef enum _ODM_RF_Config_Type{ \r
//3===========================================================\r
//3 Tx Power Tracking\r
//3===========================================================\r
-#if 0 //mask this, since these have been defined in typdef.h, vivi\r
-#define OFDM_TABLE_SIZE 43\r
-#define CCK_TABLE_SIZE 33\r
-#endif \r
+\r
\r
\r
//3===========================================================\r
RF_MAX = 2,\r
}DM_RF_E;\r
\r
-//3===========================================================\r
-//3 Antenna Diversity\r
-//3===========================================================\r
-typedef enum tag_SW_Antenna_Switch_Definition\r
-{\r
- Antenna_A = 1,\r
- Antenna_B = 2, \r
- Antenna_MAX = 3,\r
-}DM_SWAS_E;\r
-\r
-\r
-// Maximal number of antenna detection mechanism needs to perform, added by Roger, 2011.12.28.\r
-#define MAX_ANTENNA_DETECTION_CNT 10 \r
\r
//\r
// Extern Global Variables.\r
//\r
-//remove PT by YuChen\r
+//PowerTracking move to odm_powerTrakcing.h by YuChen\r
//\r
// check Sta pointer valid or not\r
//\r
#else\r
#define IS_STA_VALID(pSta) (pSta)\r
#endif\r
-// 20100514 Joseph: Add definition for antenna switching test after link.\r
-// This indicates two different the steps. \r
-// In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air.\r
-// In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK\r
-// with original RSSI to determine if it is necessary to switch antenna.\r
-#define SWAW_STEP_PEAK 0\r
-#define SWAW_STEP_DETERMINE 1\r
\r
//Remove DIG by yuchen\r
\r
-\r
-\r
-\r
//Remove BB power saving by Yuchen\r
\r
+//remove PT by yuchen\r
\r
-\r
-\r
- \r
//ODM_RAStateCheck() Remove by RS_James\r
\r
#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_AP|ODM_ADSL))\r
\r
#endif\r
\r
-#if((DM_ODM_SUPPORT_TYPE==ODM_WIN)||(DM_ODM_SUPPORT_TYPE==ODM_CE))\r
\r
-u4Byte ConvertTo_dB(u4Byte Value);\r
+\r
+u4Byte odm_ConvertTo_dB(u4Byte Value);\r
+\r
+u4Byte odm_ConvertTo_linear(u4Byte Value);\r
+\r
+#if((DM_ODM_SUPPORT_TYPE==ODM_WIN)||(DM_ODM_SUPPORT_TYPE==ODM_CE))\r
\r
u4Byte\r
GetPSDData(\r
\r
#endif\r
\r
-//Remove ODM_Get_Rate_Bitmap() by RS_James \r
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) \r
+VOID\r
+ODM_DMWatchdog_LPS(\r
+ IN PDM_ODM_T pDM_Odm\r
+);\r
+#endif\r
\r
\r
-#if (BEAMFORMING_SUPPORT == 1)\r
-BEAMFORMING_CAP\r
-Beamforming_GetEntryBeamCapByMacId(\r
- IN PMGNT_INFO pMgntInfo,\r
- IN u1Byte MacId\r
- );\r
-#endif\r
+s4Byte\r
+ODM_PWdB_Conversion(\r
+ IN s4Byte X,\r
+ IN u4Byte TotalBit,\r
+ IN u4Byte DecimalBit\r
+ );\r
+\r
+s4Byte\r
+ODM_SignConversion(\r
+ IN s4Byte value,\r
+ IN u4Byte TotalBit\r
+ );\r
\r
VOID \r
ODM_DMInit(\r
IN PDM_ODM_T pDM_Odm\r
);\r
\r
+VOID\r
+phydm_support_ablity_debug(\r
+ IN PVOID pDM_VOID,\r
+ IN u4Byte *const dm_value,\r
+ IN u4Byte *_used,\r
+ OUT char *output,\r
+ IN u4Byte *_out_len\r
+ );\r
+\r
VOID\r
ODM_DMWatchdog(\r
IN PDM_ODM_T pDM_Odm // For common use in the future\r
IN u8Byte Value \r
);\r
\r
+#if(DM_ODM_SUPPORT_TYPE==ODM_AP)\r
+VOID \r
+ODM_InitAllThreads(\r
+ IN PDM_ODM_T pDM_Odm \r
+ );\r
+\r
+VOID\r
+ODM_StopAllThreads(\r
+ IN PDM_ODM_T pDM_Odm \r
+ );\r
+#endif\r
+\r
VOID \r
ODM_InitAllTimers(\r
IN PDM_ODM_T pDM_Odm \r
VOID ODM_FreeAllWorkItems(IN PDM_ODM_T pDM_Odm );\r
\r
\r
-//===========================================//\r
-// Neil Chen----2011--06--15--\r
-\r
-//3 Path Diversity\r
-//===========================================================\r
-\r
-#define TP_MODE 0\r
-#define RSSI_MODE 1\r
-#define TRAFFIC_LOW 0\r
-#define TRAFFIC_HIGH 1\r
-\r
-//#define PATHDIV_ENABLE 1\r
-\r
-//#define dm_PathDiv_RSSI_Check ODM_PathDivChkPerPktRssi\r
\r
u8Byte\r
PlatformDivision64(\r
IN u8Byte y\r
);\r
\r
-\r
-// 20100514 Joseph: Add definition for antenna switching test after link.\r
-// This indicates two different the steps. \r
-// In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air.\r
-// In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK\r
-// with original RSSI to determine if it is necessary to switch antenna.\r
-#define SWAW_STEP_PEAK 0\r
-#define SWAW_STEP_DETERMINE 1\r
-\r
//====================================================\r
//3 PathDiV End\r
//====================================================\r
\r
-//#define PathDivCheckBeforeLink8192C ODM_PathDiversityBeforeLink92C\r
\r
#define DM_ChangeDynamicInitGainThresh ODM_ChangeDynamicInitGainThresh\r
//void ODM_ChangeDynamicInitGainThresh(IN PADAPTER pAdapter,\r
// IN INT32 DM_Type,\r
// IN INT32 DM_Value);\r
//\r
+// PathDiveristy Remove by RS_James\r
\r
typedef enum tag_DIG_Connect_Definition\r
{\r
//\r
// For new definition in MP temporarily fro power tracking,\r
//\r
+/*\r
#define odm_TXPowerTrackingDirectCall(_Adapter) \\r
IS_HARDWARE_TYPE_8192D(_Adapter) ? odm_TXPowerTrackingCallback_ThermalMeter_92D(_Adapter) : \\r
IS_HARDWARE_TYPE_8192C(_Adapter) ? odm_TXPowerTrackingCallback_ThermalMeter_92C(_Adapter) : \\r
IS_HARDWARE_TYPE_8723A(_Adapter) ? odm_TXPowerTrackingCallback_ThermalMeter_8723A(_Adapter) :\\r
ODM_TXPowerTrackingCallback_ThermalMeter(_Adapter)\r
-\r
+*/\r
\r
\r
#endif // #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
\r
-\r
-#if( DM_ODM_SUPPORT_TYPE & (ODM_WIN |ODM_CE))\r
-\r
VOID\r
-ODM_SingleDualAntennaDefaultSetting(\r
+ODM_AsocEntry_Init(\r
IN PDM_ODM_T pDM_Odm\r
);\r
\r
-BOOLEAN\r
-ODM_SingleDualAntennaDetection(\r
- IN PDM_ODM_T pDM_Odm,\r
- IN u1Byte mode\r
- );\r
+//Remove ODM_DynamicARFBSelect() by RS_James\r
\r
-#endif // #if((DM_ODM_SUPPORT_TYPE==ODM_WIN)||(DM_ODM_SUPPORT_TYPE==ODM_CE))\r
-VOID\r
-ODM_UpdateNoisyState(\r
- IN PDM_ODM_T pDM_Odm,\r
- IN BOOLEAN bNoisyStateFromC2H\r
+PVOID\r
+PhyDM_Get_Structure(\r
+ IN PDM_ODM_T pDM_Odm,\r
+ IN u1Byte Structure_Type\r
);\r
\r
-u4Byte\r
-Set_RA_DM_Ratrbitmap_by_Noisy(\r
- IN PDM_ODM_T pDM_Odm,\r
- IN WIRELESS_MODE WirelessMode,\r
- IN u4Byte ratr_bitmap,\r
- IN u1Byte rssi_level\r
-);\r
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) ||(DM_ODM_SUPPORT_TYPE == ODM_CE)\r
+/*===========================================================*/\r
+/* The following is for compile only*/\r
+/*===========================================================*/\r
\r
-VOID\r
-ODM_UpdateInitRate(\r
- IN PDM_ODM_T pDM_Odm,\r
- IN u1Byte Rate\r
- );\r
+#define IS_HARDWARE_TYPE_8723A(_Adapter) FALSE\r
+#define IS_HARDWARE_TYPE_8723AE(_Adapter) FALSE\r
+#define IS_HARDWARE_TYPE_8192C(_Adapter) FALSE\r
+#define IS_HARDWARE_TYPE_8192D(_Adapter) FALSE\r
+#define RF_T_METER_92D 0x42\r
\r
-VOID\r
-ODM_InitializeTimer(\r
- IN PDM_ODM_T pDM_Odm,\r
- IN PRT_TIMER pTimer, \r
- IN RT_TIMER_CALL_BACK CallBackFunc, \r
- IN PVOID pContext,\r
- IN const char* szID\r
-);\r
\r
-VOID\r
-ODM_CancelAllTimers(\r
- IN PDM_ODM_T pDM_Odm \r
-);\r
+#define SET_TX_DESC_ANTSEL_A_92C(__pTxDesc, __Value) SET_BITS_TO_LE_1BYTE(__pTxDesc+8+3, 0, 1, __Value)\r
+#define SET_TX_DESC_TX_ANTL_92C(__pTxDesc, __Value) SET_BITS_TO_LE_1BYTE(__pTxDesc+8+3, 4, 2, __Value)\r
+#define SET_TX_DESC_TX_ANT_HT_92C(__pTxDesc, __Value) SET_BITS_TO_LE_1BYTE(__pTxDesc+8+3, 6, 2, __Value)\r
+#define SET_TX_DESC_TX_ANT_CCK_92C(__pTxDesc, __Value) SET_BITS_TO_LE_1BYTE(__pTxDesc+8+3, 2, 2, __Value)\r
\r
-VOID\r
-ODM_ReleaseAllTimers(\r
- IN PDM_ODM_T pDM_Odm \r
-);\r
+#define GET_RX_STATUS_DESC_RX_MCS(__pRxStatusDesc) LE_BITS_TO_1BYTE( __pRxStatusDesc+12, 0, 6)\r
\r
-//Remove ODM_DynamicARFBSelect() by RS_James\r
+#define RX_HAL_IS_CCK_RATE_92C(pDesc)\\r
+ (GET_RX_STATUS_DESC_RX_MCS(pDesc) == DESC_RATE1M ||\\r
+ GET_RX_STATUS_DESC_RX_MCS(pDesc) == DESC_RATE2M ||\\r
+ GET_RX_STATUS_DESC_RX_MCS(pDesc) == DESC_RATE5_5M ||\\r
+ GET_RX_STATUS_DESC_RX_MCS(pDesc) == DESC_RATE11M)\r
\r
-PVOID\r
-PhyDM_Get_Structure(\r
- IN PDM_ODM_T pDM_Odm,\r
- IN u1Byte Structure_Type\r
+#define H2C_92C_PSD_RESULT 16\r
+\r
+#define rConfig_ram64x16 0xb2c\r
+\r
+#define TARGET_CHNL_NUM_2G_5G 59\r
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
+\r
+VOID\r
+FillH2CCmd92C( \r
+ IN PADAPTER Adapter,\r
+ IN u1Byte ElementID,\r
+ IN u4Byte CmdLen,\r
+ IN pu1Byte pCmdBuffer\r
);\r
+VOID\r
+PHY_SetTxPowerLevel8192C(\r
+ IN PADAPTER Adapter,\r
+ IN u1Byte channel\r
+ );\r
+u1Byte GetRightChnlPlaceforIQK(u1Byte chnl);\r
+\r
+#endif\r
\r
+//===========================================================\r
+#endif //#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
\r
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
void odm_dtc(PDM_ODM_T pDM_Odm);\r
projects / firefly-linux-kernel-4.4.55.git / blobdiff