--- /dev/null
+/******************************************************************************\r
+ *\r
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.\r
+ *\r
+ * This program is free software; you can redistribute it and/or modify it\r
+ * under the terms of version 2 of the GNU General Public License as\r
+ * published by the Free Software Foundation.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but WITHOUT\r
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ * more details.\r
+ *\r
+ * You should have received a copy of the GNU General Public License along with\r
+ * this program; if not, write to the Free Software Foundation, Inc.,\r
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA\r
+ *\r
+ *\r
+ ******************************************************************************/\r
+#ifndef __INC_HAL8188EPHYCFG_H__\r
+#define __INC_HAL8188EPHYCFG_H__\r
+\r
+\r
+/*--------------------------Define Parameters-------------------------------*/\r
+#define LOOP_LIMIT 5\r
+#define MAX_STALL_TIME 50 //us\r
+#define AntennaDiversityValue 0x80 //(Adapter->bSoftwareAntennaDiversity ? 0x00:0x80)\r
+#define MAX_TXPWR_IDX_NMODE_92S 63\r
+#define Reset_Cnt_Limit 3\r
+\r
+#ifdef CONFIG_PCI_HCI\r
+#define MAX_AGGR_NUM 0x0B\r
+#else\r
+#define MAX_AGGR_NUM 0x07\r
+#endif // CONFIG_PCI_HCI\r
+\r
+\r
+/*--------------------------Define Parameters-------------------------------*/\r
+\r
+\r
+/*------------------------------Define structure----------------------------*/ \r
+\r
+#define MAX_TX_COUNT_8188E 1\r
+\r
+/* BB/RF related */\r
+\r
+\r
+/*------------------------------Define structure----------------------------*/ \r
+\r
+\r
+/*------------------------Export global variable----------------------------*/\r
+/*------------------------Export global variable----------------------------*/\r
+\r
+\r
+/*------------------------Export Marco Definition---------------------------*/\r
+/*------------------------Export Marco Definition---------------------------*/\r
+\r
+\r
+/*--------------------------Exported Function prototype---------------------*/\r
+//\r
+// BB and RF register read/write\r
+//\r
+u32 PHY_QueryBBReg8188E( IN PADAPTER Adapter,\r
+ IN u32 RegAddr,\r
+ IN u32 BitMask );\r
+void PHY_SetBBReg8188E( IN PADAPTER Adapter,\r
+ IN u32 RegAddr,\r
+ IN u32 BitMask,\r
+ IN u32 Data );\r
+u32 PHY_QueryRFReg8188E( IN PADAPTER Adapter,\r
+ IN u8 eRFPath,\r
+ IN u32 RegAddr,\r
+ IN u32 BitMask );\r
+void PHY_SetRFReg8188E( IN PADAPTER Adapter,\r
+ IN u8 eRFPath,\r
+ IN u32 RegAddr,\r
+ IN u32 BitMask,\r
+ IN u32 Data );\r
+\r
+//\r
+// Initialization related function\r
+//\r
+/* MAC/BB/RF HAL config */\r
+int PHY_MACConfig8188E(IN PADAPTER Adapter );\r
+int PHY_BBConfig8188E(IN PADAPTER Adapter );\r
+int PHY_RFConfig8188E(IN PADAPTER Adapter );\r
+\r
+/* RF config */\r
+int rtl8188e_PHY_ConfigRFWithParaFile(IN PADAPTER Adapter, IN u8 * pFileName, u8 eRFPath);\r
+\r
+//\r
+// RF Power setting\r
+//\r
+//extern BOOLEAN PHY_SetRFPowerState(IN PADAPTER Adapter, \r
+// IN RT_RF_POWER_STATE eRFPowerState);\r
+\r
+//\r
+// BB TX Power R/W\r
+//\r
+void PHY_GetTxPowerLevel8188E( IN PADAPTER Adapter,\r
+ OUT s32* powerlevel );\r
+void PHY_SetTxPowerLevel8188E( IN PADAPTER Adapter,\r
+ IN u8 channel );\r
+BOOLEAN PHY_UpdateTxPowerDbm8188E( IN PADAPTER Adapter,\r
+ IN int powerInDbm );\r
+\r
+VOID\r
+PHY_SetTxPowerIndex_8188E(\r
+ IN PADAPTER Adapter,\r
+ IN u32 PowerIndex,\r
+ IN u8 RFPath, \r
+ IN u8 Rate\r
+ );\r
+\r
+u8\r
+PHY_GetTxPowerIndex_8188E(\r
+ IN PADAPTER pAdapter,\r
+ IN u8 RFPath,\r
+ IN u8 Rate, \r
+ IN CHANNEL_WIDTH BandWidth, \r
+ IN u8 Channel\r
+ );\r
+\r
+//\r
+// Switch bandwidth for 8192S\r
+//\r
+//extern void PHY_SetBWModeCallback8192C( IN PRT_TIMER pTimer );\r
+void PHY_SetBWMode8188E( IN PADAPTER pAdapter,\r
+ IN CHANNEL_WIDTH ChnlWidth,\r
+ IN unsigned char Offset );\r
+\r
+//\r
+// Set FW CMD IO for 8192S.\r
+//\r
+//extern BOOLEAN HalSetIO8192C( IN PADAPTER Adapter,\r
+// IN IO_TYPE IOType);\r
+\r
+//\r
+// Set A2 entry to fw for 8192S\r
+//\r
+extern void FillA2Entry8192C( IN PADAPTER Adapter,\r
+ IN u8 index,\r
+ IN u8* val);\r
+\r
+\r
+//\r
+// channel switch related funciton\r
+//\r
+//extern void PHY_SwChnlCallback8192C( IN PRT_TIMER pTimer );\r
+void PHY_SwChnl8188E( IN PADAPTER pAdapter,\r
+ IN u8 channel );\r
+\r
+VOID\r
+PHY_SetSwChnlBWMode8188E(\r
+ IN PADAPTER Adapter,\r
+ IN u8 channel,\r
+ IN CHANNEL_WIDTH Bandwidth,\r
+ IN u8 Offset40,\r
+ IN u8 Offset80\r
+);\r
+\r
+VOID\r
+PHY_SetRFEReg_8188E(\r
+ IN PADAPTER Adapter\r
+);\r
+//\r
+// BB/MAC/RF other monitor API\r
+//\r
+void PHY_SetMonitorMode8192C(IN PADAPTER pAdapter,\r
+ IN BOOLEAN bEnableMonitorMode );\r
+\r
+BOOLEAN PHY_CheckIsLegalRfPath8192C(IN PADAPTER pAdapter,\r
+ IN u32 eRFPath );\r
+\r
+VOID PHY_SetRFPathSwitch_8188E(IN PADAPTER pAdapter, IN BOOLEAN bMain);\r
+\r
+extern VOID\r
+PHY_SwitchEphyParameter(\r
+ IN PADAPTER Adapter\r
+ );\r
+\r
+extern VOID\r
+PHY_EnableHostClkReq(\r
+ IN PADAPTER Adapter\r
+ );\r
+\r
+BOOLEAN\r
+SetAntennaConfig92C(\r
+ IN PADAPTER Adapter,\r
+ IN u8 DefaultAnt \r
+ );\r
+\r
+VOID\r
+storePwrIndexDiffRateOffset(\r
+ IN PADAPTER Adapter,\r
+ IN u32 RegAddr,\r
+ IN u32 BitMask,\r
+ IN u32 Data\r
+ );\r
+/*--------------------------Exported Function prototype---------------------*/\r
+\r
+//\r
+// Initialization related function\r
+//\r
+/* MAC/BB/RF HAL config */\r
+//extern s32 PHY_MACConfig8723(PADAPTER padapter);\r
+//s32 PHY_BBConfig8723(PADAPTER padapter);\r
+//s32 PHY_RFConfig8723(PADAPTER padapter);\r
+\r
+\r
+\r
+//==================================================================\r
+// Note: If SIC_ENABLE under PCIE, because of the slow operation\r
+// you should \r
+// 2) "#define RTL8723_FPGA_VERIFICATION 1" in Precomp.h.WlanE.Windows\r
+// 3) "#define RTL8190_Download_Firmware_From_Header 0" in Precomp.h.WlanE.Windows if needed.\r
+//\r
+#if (RTL8188E_SUPPORT == 1) && (RTL8188E_FPGA_TRUE_PHY_VERIFICATION == 1)\r
+#define SIC_ENABLE 1\r
+#define SIC_HW_SUPPORT 1\r
+#else\r
+#define SIC_ENABLE 0\r
+#define SIC_HW_SUPPORT 0\r
+#endif\r
+//==================================================================\r
+\r
+\r
+#define SIC_MAX_POLL_CNT 5\r
+\r
+#if(SIC_HW_SUPPORT == 1)\r
+#define SIC_CMD_READY 0\r
+#define SIC_CMD_PREWRITE 0x1\r
+#if(RTL8188E_SUPPORT == 1)\r
+#define SIC_CMD_WRITE 0x40\r
+#define SIC_CMD_PREREAD 0x2\r
+#define SIC_CMD_READ 0x80\r
+#define SIC_CMD_INIT 0xf0\r
+#define SIC_INIT_VAL 0xff\r
+\r
+#define SIC_INIT_REG 0x1b7\r
+#define SIC_CMD_REG 0x1EB // 1byte\r
+#define SIC_ADDR_REG 0x1E8 // 1b4~1b5, 2 bytes\r
+#define SIC_DATA_REG 0x1EC // 1b0~1b3\r
+#else\r
+#define SIC_CMD_WRITE 0x11\r
+#define SIC_CMD_PREREAD 0x2\r
+#define SIC_CMD_READ 0x12\r
+#define SIC_CMD_INIT 0x1f\r
+#define SIC_INIT_VAL 0xff\r
+\r
+#define SIC_INIT_REG 0x1b7\r
+#define SIC_CMD_REG 0x1b6 // 1byte\r
+#define SIC_ADDR_REG 0x1b4 // 1b4~1b5, 2 bytes\r
+#define SIC_DATA_REG 0x1b0 // 1b0~1b3\r
+#endif\r
+#else\r
+#define SIC_CMD_READY 0\r
+#define SIC_CMD_WRITE 1\r
+#define SIC_CMD_READ 2\r
+\r
+#if(RTL8188E_SUPPORT == 1)\r
+#define SIC_CMD_REG 0x1EB // 1byte\r
+#define SIC_ADDR_REG 0x1E8 // 1b9~1ba, 2 bytes\r
+#define SIC_DATA_REG 0x1EC // 1bc~1bf\r
+#else\r
+#define SIC_CMD_REG 0x1b8 // 1byte\r
+#define SIC_ADDR_REG 0x1b9 // 1b9~1ba, 2 bytes\r
+#define SIC_DATA_REG 0x1bc // 1bc~1bf\r
+#endif\r
+#endif\r
+\r
+#if(SIC_ENABLE == 1)\r
+VOID SIC_Init(IN PADAPTER Adapter);\r
+#endif\r
+\r
+\r
+#endif // __INC_HAL8192CPHYCFG_H\r
+\r
projects / firefly-linux-kernel-4.4.55.git / blobdiff