return ret;
}
-int scpi_ddr_init(u32 dram_speed_bin, u32 freq)
+int scpi_sys_set_mcu_state_suspend(void)
+{
+ struct scpi_data_buf sdata;
+ struct rockchip_mbox_msg mdata;
+ struct __packed1 {
+ u32 status;
+ } tx_buf;
+ struct __packed2 {
+ u32 status;
+ } rx_buf;
+
+ tx_buf.status = 0;
+ SCPI_SETUP_DBUF(sdata, mdata, SCPI_CL_SYS,
+ SCPI_SYS_SET_MCU_STATE_SUSPEND, tx_buf, rx_buf);
+ return scpi_execute_cmd(&sdata);
+}
+EXPORT_SYMBOL_GPL(scpi_sys_set_mcu_state_suspend);
+
+int scpi_sys_set_mcu_state_resume(void)
+{
+ struct scpi_data_buf sdata;
+ struct rockchip_mbox_msg mdata;
+ struct __packed1 {
+ u32 status;
+ } tx_buf;
+ struct __packed2 {
+ u32 status;
+ } rx_buf;
+
+ tx_buf.status = 0;
+
+ SCPI_SETUP_DBUF(sdata, mdata, SCPI_CL_SYS,
+ SCPI_SYS_SET_MCU_STATE_RESUME, tx_buf, rx_buf);
+ return scpi_execute_cmd(&sdata);
+}
+EXPORT_SYMBOL_GPL(scpi_sys_set_mcu_state_resume);
+
+int scpi_ddr_init(u32 dram_speed_bin, u32 freq, u32 lcdc_type)
{
struct scpi_data_buf sdata;
struct rockchip_mbox_msg mdata;
struct __packed1 {
u32 dram_speed_bin;
u32 freq;
+ u32 lcdc_type;
} tx_buf;
struct __packed2 {
u32 status;
tx_buf.dram_speed_bin = (u32)dram_speed_bin;
tx_buf.freq = (u32)freq;
+ tx_buf.lcdc_type = (u32)lcdc_type;
SCPI_SETUP_DBUF(sdata, mdata, SCPI_CL_DDR,
SCPI_DDR_INIT, tx_buf, rx_buf);
return ret;
}
-static struct platform_driver mobx_scpi_driver = {
+static struct platform_driver mbox_scpi_driver = {
.probe = mobx_scpi_probe,
.driver = {
.name = "mbox-scpi",
.of_match_table = of_match_ptr(mobx_scpi_of_match),
},
};
-module_platform_driver(mobx_scpi_driver);
-MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>");
-MODULE_DESCRIPTION("Rockchip SCPI Driver");
-MODULE_LICENSE("GPL v2");
+static int __init rockchip_mbox_scpi_init(void)
+{
+ return platform_driver_register(&mbox_scpi_driver);
+}
+subsys_initcall(rockchip_mbox_scpi_init);