clk: rockchip: support setting ddr clock via SCPI APIs

[firefly-linux-kernel-4.4.55.git] / drivers / clk / rockchip / clk.h

diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h
index 70e825282b716f43654e000d9972dd83a2147391..c1e49b2767ec46d1343e184e4c49699442ae4b6b 100644 (file)
--- a/drivers/clk/rockchip/clk.h
+++ b/drivers/clk/rockchip/clk.h
@@ -86,10 +86,6 @@ struct clk;
 #define RK3328_SOFTRST_CON(x)          ((x) * 0x4 + 0x300)
 #define RK3328_MODE_CON                        0x80
 #define RK3328_MISC_CON                        0x84
-#define RK3328_DIV_ACLKM_MASK          0x7
-#define RK3328_DIV_ACLKM_SHIFT         4
-#define RK3328_DIV_PCLK_DBG_MASK       0xf
-#define RK3328_DIV_PCLK_DBG_SHIFT      0
 #define RK3328_SDMMC_CON0              0x380
 #define RK3328_SDMMC_CON1              0x384
 #define RK3328_SDIO_CON0               0x388
@@ -313,8 +309,10 @@ struct clk *rockchip_clk_register_mmc(const char *name,
  * there may have serval ways to set ddr clock, use
  * this flag to distinguish them.
  * ROCKCHIP_DDRCLK_SIP: use SIP call to bl31 to change ddrclk rate.
+ * ROCKCHIP_DDRCLK_SCPI: use SCPI APIs to let mcu change ddrclk rate.
  */
 #define ROCKCHIP_DDRCLK_SIP            0x01
+#define ROCKCHIP_DDRCLK_SCPI           0x02
 
 struct clk *rockchip_clk_register_ddrclk(const char *name, int flags,
                                         const char *const *parent_names,