clk: rockchip: support setting ddr clock via SCPI APIs

[firefly-linux-kernel-4.4.55.git] / drivers / clk / rockchip / clk.h

diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h
index 524626e6cbc988465bd0dc09bd8087c8f69fd103..c1e49b2767ec46d1343e184e4c49699442ae4b6b 100644 (file)
--- a/drivers/clk/rockchip/clk.h
+++ b/drivers/clk/rockchip/clk.h
@@ -34,7 +34,7 @@ struct clk;
 #define HIWORD_UPDATE(val, mask, shift) \
                ((val) << (shift) | (mask) << ((shift) + 16))
 
-/* register positions shared by RK2928, RK3036, RK3066 and RK3188 */
+/* register positions shared by RK2928, RK3036, RK3066, RK3188 and RK3228 */
 #define RK2928_PLL_CON(x)              ((x) * 0x4)
 #define RK2928_MODE_CON                0x40
 #define RK2928_CLKSEL_CON(x)   ((x) * 0x4 + 0x44)
@@ -51,6 +51,15 @@ struct clk;
 #define RK3036_EMMC_CON0               0x154
 #define RK3036_EMMC_CON1               0x158
 
+#define RK3228_GLB_SRST_FST            0x1f0
+#define RK3228_GLB_SRST_SND            0x1f4
+#define RK3228_SDMMC_CON0              0x1c0
+#define RK3228_SDMMC_CON1              0x1c4
+#define RK3228_SDIO_CON0               0x1c8
+#define RK3228_SDIO_CON1               0x1cc
+#define RK3228_EMMC_CON0               0x1d8
+#define RK3228_EMMC_CON1               0x1dc
+
 #define RK3288_PLL_CON(x)              RK2928_PLL_CON(x)
 #define RK3288_MODE_CON                        0x50
 #define RK3288_CLKSEL_CON(x)           ((x) * 0x4 + 0x60)
@@ -68,6 +77,24 @@ struct clk;
 #define RK3288_EMMC_CON0               0x218
 #define RK3288_EMMC_CON1               0x21c
 
+#define RK3328_PLL_CON(x)              RK2928_PLL_CON(x)
+#define RK3328_CLKSEL_CON(x)           ((x) * 0x4 + 0x100)
+#define RK3328_CLKGATE_CON(x)          ((x) * 0x4 + 0x200)
+#define RK3328_GRFCLKSEL_CON(x)                ((x) * 0x4 + 0x100)
+#define RK3328_GLB_SRST_FST            0x9c
+#define RK3328_GLB_SRST_SND            0x98
+#define RK3328_SOFTRST_CON(x)          ((x) * 0x4 + 0x300)
+#define RK3328_MODE_CON                        0x80
+#define RK3328_MISC_CON                        0x84
+#define RK3328_SDMMC_CON0              0x380
+#define RK3328_SDMMC_CON1              0x384
+#define RK3328_SDIO_CON0               0x388
+#define RK3328_SDIO_CON1               0x38c
+#define RK3328_EMMC_CON0               0x390
+#define RK3328_EMMC_CON1               0x394
+#define RK3328_SDMMC_EXT_CON0          0x398
+#define RK3328_SDMMC_EXT_CON1          0x39C
+
 #define RK3368_PLL_CON(x)              RK2928_PLL_CON(x)
 #define RK3368_CLKSEL_CON(x)           ((x) * 0x4 + 0x100)
 #define RK3368_CLKGATE_CON(x)          ((x) * 0x4 + 0x200)
@@ -109,6 +136,7 @@ struct clk;
 enum rockchip_pll_type {
        pll_rk3036,
        pll_rk3066,
+       pll_rk3328,
        pll_rk3366,
        pll_rk3399,
 };
@@ -233,7 +261,7 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx,
                u8 num_parents, int con_offset, int grf_lock_offset,
                int lock_shift, int mode_offset, int mode_shift,
                struct rockchip_pll_rate_table *rate_table,
-               u8 clk_pll_flags);
+               unsigned long flags, u8 clk_pll_flags);
 
 struct rockchip_cpuclk_clksel {
        int reg;
@@ -276,6 +304,24 @@ struct clk *rockchip_clk_register_mmc(const char *name,
                                const char *const *parent_names, u8 num_parents,
                                void __iomem *reg, int shift);
 
+/*
+ * for COMPOSITE_DDRCLK div_flag,
+ * there may have serval ways to set ddr clock, use
+ * this flag to distinguish them.
+ * ROCKCHIP_DDRCLK_SIP: use SIP call to bl31 to change ddrclk rate.
+ * ROCKCHIP_DDRCLK_SCPI: use SCPI APIs to let mcu change ddrclk rate.
+ */
+#define ROCKCHIP_DDRCLK_SIP            0x01
+#define ROCKCHIP_DDRCLK_SCPI           0x02
+
+struct clk *rockchip_clk_register_ddrclk(const char *name, int flags,
+                                        const char *const *parent_names,
+                                        u8 num_parents, int mux_offset,
+                                        int mux_shift, int mux_width,
+                                        int div_shift, int div_width,
+                                        int ddr_flags, void __iomem *reg_base,
+                                        spinlock_t *lock);
+
 #define ROCKCHIP_INVERTER_HIWORD_MASK  BIT(0)
 
 struct clk *rockchip_clk_register_inverter(const char *name,
@@ -283,17 +329,24 @@ struct clk *rockchip_clk_register_inverter(const char *name,
                                void __iomem *reg, int shift, int flags,
                                spinlock_t *lock);
 
+struct clk *rockchip_clk_register_muxgrf(const char *name,
+                               const char *const *parent_names, u8 num_parents,
+                               int flags, struct regmap *grf, int reg,
+                               int shift, int width, int mux_flags);
+
 #define PNAME(x) static const char *const x[] __initconst
 
 enum rockchip_clk_branch_type {
        branch_composite,
        branch_mux,
+       branch_muxgrf,
        branch_divider,
        branch_fraction_divider,
        branch_gate,
        branch_mmc,
        branch_inverter,
        branch_factor,
+       branch_ddrc,
 };
 
 struct rockchip_clk_branch {
@@ -483,6 +536,24 @@ struct rockchip_clk_branch {
                .child          = ch,                           \
        }
 
+#define COMPOSITE_DDRCLK(_id, cname, pnames, f, mo, ms, mw,    \
+                        ds, dw, df)                            \
+       {                                                       \
+               .id             = _id,                          \
+               .branch_type    = branch_ddrc,                  \
+               .name           = cname,                        \
+               .parent_names   = pnames,                       \
+               .num_parents    = ARRAY_SIZE(pnames),           \
+               .flags          = f,                            \
+               .muxdiv_offset  = mo,                           \
+               .mux_shift      = ms,                           \
+               .mux_width      = mw,                           \
+               .div_shift      = ds,                           \
+               .div_width      = dw,                           \
+               .div_flags      = df,                           \
+               .gate_offset    = -1,                           \
+       }
+
 #define MUX(_id, cname, pnames, f, o, s, w, mf)                        \
        {                                                       \
                .id             = _id,                          \
@@ -498,6 +569,21 @@ struct rockchip_clk_branch {
                .gate_offset    = -1,                           \
        }
 
+#define MUXGRF(_id, cname, pnames, f, o, s, w, mf)             \
+       {                                                       \
+               .id             = _id,                          \
+               .branch_type    = branch_muxgrf,                \
+               .name           = cname,                        \
+               .parent_names   = pnames,                       \
+               .num_parents    = ARRAY_SIZE(pnames),           \
+               .flags          = f,                            \
+               .muxdiv_offset  = o,                            \
+               .mux_shift      = s,                            \
+               .mux_width      = w,                            \
+               .mux_flags      = mf,                           \
+               .gate_offset    = -1,                           \
+       }
+
 #define DIV(_id, cname, pname, f, o, s, w, df)                 \
        {                                                       \
                .id             = _id,                          \