clk: rockchip: rk3368: add ddrc clock support

[firefly-linux-kernel-4.4.55.git] / drivers / clk / rockchip / clk-rk3368.c

diff --git a/drivers/clk/rockchip/clk-rk3368.c b/drivers/clk/rockchip/clk-rk3368.c
index 86dd3646fd7c5b3db152e2ff6a25074ffffbe8f6..a5e5050e4ccf07283477381f850cac826afed59c 100644 (file)
--- a/drivers/clk/rockchip/clk-rk3368.c
+++ b/drivers/clk/rockchip/clk-rk3368.c
@@ -338,6 +338,9 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
                        RK3368_CLKGATE_CON(1), 8, GFLAGS),
        GATE(0, "gpll_ddr", "gpll", 0,
                        RK3368_CLKGATE_CON(1), 9, GFLAGS),
+       COMPOSITE_DDRCLK(SCLK_DDRCLK, "sclk_ddrc", mux_ddrphy_p, 0,
+                       RK3368_CLKSEL_CON(13), 4, 1, 0, 0, ROCKCHIP_DDRCLK_SCPI),
+
        COMPOSITE_NOGATE_DIVTBL(0, "ddrphy_src", mux_ddrphy_p, CLK_IGNORE_UNUSED,
                        RK3368_CLKSEL_CON(13), 4, 1, MFLAGS, 0, 2, DFLAGS, div_ddrphy_t),
 
@@ -538,7 +541,8 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
        GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", CLK_IGNORE_UNUSED,
                        RK3368_CLKGATE_CON(3), 1, GFLAGS),
 
-       GATE(SCLK_MIPIDSI_24M, "sclk_mipidsi_24m", "xin24m", 0, RK3368_CLKGATE_CON(4), 14, GFLAGS),
+       GATE(SCLK_MIPIDSI_24M, "sclk_mipidsi_24m", "xin24m", CLK_IGNORE_UNUSED,
+                       RK3368_CLKGATE_CON(4), 14, GFLAGS),
 
        /*
         * Clock-Architecture Diagram 4
@@ -859,6 +863,7 @@ static const char *const rk3368_critical_clocks[] __initconst = {
        "aclk_bus",
        "aclk_peri",
        "pclk_pd_pmu",
+       "hclk_vio_noc",
 };
 
 static void __init rk3368_clk_init(struct device_node *np)