UPSTREAM: arm64: dts: rockchip: add three new resets for rk3399 PCIe

[firefly-linux-kernel-4.4.55.git] / arch / arm64 / boot / dts / rockchip / rk3399.dtsi

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index e9efa42d4b3674a5a100ea1d8d6827830981d89f..baeaed53cd4d9eca83c11589aaa8864b009515d6 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -118,7 +118,7 @@
                        #cooling-cells = <2>; /* min followed by max */
                        dynamic-power-coefficient = <100>;
                        clocks = <&cru ARMCLKL>;
-                       cpu-idle-states = <&cpu_sleep>;
+                       cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
                        operating-points-v2 = <&cluster0_opp>;
                        sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
                };
@@ -129,7 +129,7 @@
                        reg = <0x0 0x1>;
                        enable-method = "psci";
                        clocks = <&cru ARMCLKL>;
-                       cpu-idle-states = <&cpu_sleep>;
+                       cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
                        operating-points-v2 = <&cluster0_opp>;
                        sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
                };
@@ -140,7 +140,7 @@
                        reg = <0x0 0x2>;
                        enable-method = "psci";
                        clocks = <&cru ARMCLKL>;
-                       cpu-idle-states = <&cpu_sleep>;
+                       cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
                        operating-points-v2 = <&cluster0_opp>;
                        sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
                };
@@ -151,7 +151,7 @@
                        reg = <0x0 0x3>;
                        enable-method = "psci";
                        clocks = <&cru ARMCLKL>;
-                       cpu-idle-states = <&cpu_sleep>;
+                       cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
                        operating-points-v2 = <&cluster0_opp>;
                        sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
                };
@@ -164,7 +164,7 @@
                        #cooling-cells = <2>; /* min followed by max */
                        dynamic-power-coefficient = <436>;
                        clocks = <&cru ARMCLKB>;
-                       cpu-idle-states = <&cpu_sleep>;
+                       cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
                        operating-points-v2 = <&cluster1_opp>;
                        sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
                };
@@ -175,20 +175,30 @@
                        reg = <0x0 0x101>;
                        enable-method = "psci";
                        clocks = <&cru ARMCLKB>;
-                       cpu-idle-states = <&cpu_sleep>;
+                       cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
                        operating-points-v2 = <&cluster1_opp>;
                        sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
                };
 
                idle-states {
                        entry-method = "psci";
-                       cpu_sleep: cpu-sleep-0 {
+
+                       CPU_SLEEP: cpu-sleep {
                                compatible = "arm,idle-state";
                                local-timer-stop;
                                arm,psci-suspend-param = <0x0010000>;
-                               entry-latency-us = <350>;
-                               exit-latency-us = <600>;
-                               min-residency-us = <1150>;
+                               entry-latency-us = <120>;
+                               exit-latency-us = <250>;
+                               min-residency-us = <900>;
+                       };
+
+                       CLUSTER_SLEEP: cluster-sleep {
+                               compatible = "arm,idle-state";
+                               local-timer-stop;
+                               arm,psci-suspend-param = <0x1010000>;
+                               entry-latency-us = <400>;
+                               exit-latency-us = <500>;
+                               min-residency-us = <2000>;
                        };
                };
 
@@ -548,6 +558,8 @@
                #io-channel-cells = <1>;
                clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
                clock-names = "saradc", "apb_pclk";
+               resets = <&cru SRST_P_SARADC>;
+               reset-names = "saradc-apb";
                status = "disabled";
        };
 
@@ -1081,6 +1093,16 @@
                                        pm_qos = <&qos_isp1_m0>,
                                                 <&qos_isp1_m1>;
                                };
+                               pd_tcpc0@RK3399_PD_TCPC0 {
+                                       reg = <RK3399_PD_TCPD0>;
+                                       clocks = <&cru SCLK_UPHY0_TCPDCORE>,
+                                                <&cru SCLK_UPHY0_TCPDPHY_REF>;
+                               };
+                               pd_tcpc1@RK3399_PD_TCPC1 {
+                                       reg = <RK3399_PD_TCPD1>;
+                                       clocks = <&cru SCLK_UPHY1_TCPDCORE>,
+                                                <&cru SCLK_UPHY1_TCPDPHY_REF>;
+                               };
                                pd_vo@RK3399_PD_VO {
                                        reg = <RK3399_PD_VO>;
                                        #address-cells = <1>;
@@ -1119,6 +1141,13 @@
                        mode-recovery = <BOOT_RECOVERY>;
                        mode-ums = <BOOT_UMS>;
                };
+
+               pmu_pvtm: pmu-pvtm {
+                       compatible = "rockchip,rk3399-pmu-pvtm";
+                       clocks = <&pmucru SCLK_PVTM_PMU>;
+                       clock-names = "pmu";
+                       status = "disabled";
+               };
        };
 
        spi3: spi@ff350000 {
@@ -1212,8 +1241,11 @@
                      <0x0 0xfd000000 0x0 0x1000000>;
                reg-names = "axi-base", "apb-base";
                resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
-                        <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>;
-               reset-names = "core", "mgmt", "mgmt-sticky", "pipe";
+                        <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,
+                        <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>,
+                        <&cru SRST_A_PCIE>;
+               reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
+                             "pm", "pclk", "aclk";
                status = "disabled";
                pcie0_intc: interrupt-controller {
                        interrupt-controller;
@@ -1356,7 +1388,7 @@
                        <&cru ACLK_VOP1>, <&cru HCLK_VOP1>,
                        <&cru ARMCLKL>, <&cru ARMCLKB>,
                        <&cru PLL_GPLL>, <&cru PLL_CPLL>,
-                       <&cru PLL_NPLL>,
+                       <&cru ACLK_GPU>, <&cru PLL_NPLL>,
                        <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
                        <&cru PCLK_PERIHP>,
                        <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
@@ -1367,7 +1399,7 @@
                         <400000000>,  <200000000>,
                         <816000000>, <816000000>,
                         <594000000>,  <800000000>,
-                       <1000000000>,
+                        <200000000>, <1000000000>,
                         <150000000>,   <75000000>,
                          <37500000>,
                         <100000000>,  <100000000>,
@@ -1443,6 +1475,16 @@
                                status = "disabled";
                        };
                };
+
+               pvtm: pvtm {
+                       compatible = "rockchip,rk3399-pvtm";
+                       clocks = <&cru SCLK_PVTM_CORE_L>,
+                                <&cru SCLK_PVTM_CORE_B>,
+                                <&cru SCLK_PVTM_GPU>,
+                                <&cru SCLK_PVTM_DDR>;
+                       clock-names = "core_l", "core_b", "gpu", "ddr";
+                       status = "disabled";
+               };
        };
 
        tcphy0: phy@ff7c0000 {
@@ -1455,6 +1497,7 @@
                clock-names = "tcpdcore", "tcpdphy-ref";
                assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
                assigned-clock-rates = <50000000>;
+               power-domains = <&power RK3399_PD_TCPD0>;
                resets = <&cru SRST_UPHY0>,
                         <&cru SRST_UPHY0_PIPE_L00>,
                         <&cru SRST_P_UPHY0_TCPHY>;
@@ -1487,6 +1530,7 @@
                clock-names = "tcpdcore", "tcpdphy-ref";
                assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
                assigned-clock-rates = <50000000>;
+               power-domains = <&power RK3399_PD_TCPD1>;
                resets = <&cru SRST_UPHY1>,
                         <&cru SRST_UPHY1_PIPE_L00>,
                         <&cru SRST_P_UPHY1_TCPHY>;