#include <dt-bindings/soc/rockchip_boot-mode.h>
#include <dt-bindings/thermal/thermal.h>
+#include "rk3399-dram-default-timing.dtsi"
+
/ {
compatible = "rockchip,rk3399";
#cooling-cells = <2>; /* min followed by max */
dynamic-power-coefficient = <100>;
clocks = <&cru ARMCLKL>;
- cpu-idle-states = <&cpu_sleep>;
+ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
operating-points-v2 = <&cluster0_opp>;
sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
};
reg = <0x0 0x1>;
enable-method = "psci";
clocks = <&cru ARMCLKL>;
- cpu-idle-states = <&cpu_sleep>;
+ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
operating-points-v2 = <&cluster0_opp>;
sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
};
reg = <0x0 0x2>;
enable-method = "psci";
clocks = <&cru ARMCLKL>;
- cpu-idle-states = <&cpu_sleep>;
+ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
operating-points-v2 = <&cluster0_opp>;
sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
};
reg = <0x0 0x3>;
enable-method = "psci";
clocks = <&cru ARMCLKL>;
- cpu-idle-states = <&cpu_sleep>;
+ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
operating-points-v2 = <&cluster0_opp>;
sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
};
#cooling-cells = <2>; /* min followed by max */
dynamic-power-coefficient = <436>;
clocks = <&cru ARMCLKB>;
- cpu-idle-states = <&cpu_sleep>;
+ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
operating-points-v2 = <&cluster1_opp>;
sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
};
reg = <0x0 0x101>;
enable-method = "psci";
clocks = <&cru ARMCLKB>;
- cpu-idle-states = <&cpu_sleep>;
+ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
operating-points-v2 = <&cluster1_opp>;
sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
};
idle-states {
entry-method = "psci";
- cpu_sleep: cpu-sleep-0 {
+
+ CPU_SLEEP: cpu-sleep {
compatible = "arm,idle-state";
local-timer-stop;
arm,psci-suspend-param = <0x0010000>;
- entry-latency-us = <350>;
- exit-latency-us = <600>;
- min-residency-us = <1150>;
+ entry-latency-us = <120>;
+ exit-latency-us = <250>;
+ min-residency-us = <900>;
+ };
+
+ CLUSTER_SLEEP: cluster-sleep {
+ compatible = "arm,idle-state";
+ local-timer-stop;
+ arm,psci-suspend-param = <0x1010000>;
+ entry-latency-us = <400>;
+ exit-latency-us = <500>;
+ min-residency-us = <2000>;
};
};
};
};
+ cpu_avs: cpu-avs {
+ cluster0-avs {
+ cluster-id = <0>;
+ min-volt = <800000>; /* uV */
+ min-freq = <408000>; /* KHz */
+ leakage-adjust-volt = <
+ /* mA mA uV */
+ 0 254 0
+ >;
+ nvmem-cells = <&cpul_leakage>;
+ nvmem-cell-names = "cpu_leakage";
+ };
+ cluster1-avs {
+ cluster-id = <1>;
+ min-volt = <800000>; /* uV */
+ min-freq = <408000>; /* KHz */
+ leakage-adjust-volt = <
+ /* mA mA uV */
+ 0 254 0
+ >;
+ nvmem-cells = <&cpub_leakage>;
+ nvmem-cell-names = "cpu_leakage";
+ };
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
"pclk_mac";
resets = <&cru SRST_A_GMAC>;
reset-names = "stmmaceth";
- status = "disabled";
- };
-
- emmc_phy: phy {
- compatible = "rockchip,rk3399-emmc-phy";
- reg-offset = <0xf780>;
- #phy-cells = <0>;
- rockchip,grf = <&grf>;
- ctrl-base = <0xfe330000>;
+ power-domains = <&power RK3399_PD_GMAC>;
status = "disabled";
};
compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
reg = <0x0 0xfe330000 0x0 0x10000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
- clock-names = "clk_xin", "clk_ahb";
+ arasan,soc-ctl-syscon = <&grf>;
assigned-clocks = <&cru SCLK_EMMC>;
- assigned-clock-parents = <&cru PLL_CPLL>;
assigned-clock-rates = <200000000>;
+ clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
+ clock-names = "clk_xin", "clk_ahb";
+ clock-output-names = "emmc_cardclock";
+ #clock-cells = <0>;
phys = <&emmc_phy>;
phy-names = "phy_arasan";
power-domains = <&power RK3399_PD_EMMC>;
};
usbdrd3_0: usb@fe800000 {
- compatible = "rockchip,dwc3";
+ compatible = "rockchip,rk3399-dwc3";
clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
- <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
- <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
- clock-names = "clk_usb3otg0_ref", "clk_usb3otg0_suspend",
- "aclk_usb3otg0", "aclk_usb3_rksoc_axi_perf",
- "aclk_usb3", "aclk_usb3_grf";
+ <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>;
+ clock-names = "ref_clk", "suspend_clk",
+ "bus_clk", "grf_clk";
+ power-domains = <&power RK3399_PD_USB3>;
+ resets = <&cru SRST_A_USB3_OTG0>;
+ reset-names = "usb3-otg";
#address-cells = <2>;
#size-cells = <2>;
ranges;
reg = <0x0 0xfe800000 0x0 0x100000>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
dr_mode = "otg";
- phys = <&u2phy0_otg>;
- phy-names = "usb2-phy";
+ phys = <&u2phy0_otg>, <&tcphy0_usb3>;
+ phy-names = "usb2-phy", "usb3-phy";
+ phy_type = "utmi_wide";
snps,dis_enblslpm_quirk;
- snps,phyif_utmi_16_bits;
- snps,dis_u2_freeclk_exists_quirk;
- snps,dis_del_phy_power_chg_quirk;
- snps,xhci_slow_suspend_quirk;
+ snps,dis-u2-freeclk-exists-quirk;
+ snps,dis_u2_susphy_quirk;
+ snps,dis-del-phy-power-chg-quirk;
+ snps,xhci-slow-suspend-quirk;
status = "disabled";
};
};
usbdrd3_1: usb@fe900000 {
- compatible = "rockchip,dwc3";
+ compatible = "rockchip,rk3399-dwc3";
clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
- <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
- <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
- clock-names = "clk_usb3otg1_ref", "clk_usb3otg1_suspend",
- "aclk_usb3otg1", "aclk_usb3_rksoc_axi_perf",
- "aclk_usb3", "aclk_usb3_grf";
+ <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_GRF>;
+ clock-names = "ref_clk", "suspend_clk",
+ "bus_clk", "grf_clk";
+ power-domains = <&power RK3399_PD_USB3>;
+ resets = <&cru SRST_A_USB3_OTG1>;
+ reset-names = "usb3-otg";
#address-cells = <2>;
#size-cells = <2>;
ranges;
compatible = "snps,dwc3";
reg = <0x0 0xfe900000 0x0 0x100000>;
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
- dr_mode = "otg";
- phys = <&u2phy1_otg>;
- phy-names = "usb2-phy";
+ dr_mode = "host";
+ phys = <&u2phy1_otg>, <&tcphy1_usb3>;
+ phy-names = "usb2-phy", "usb3-phy";
+ phy_type = "utmi_wide";
snps,dis_enblslpm_quirk;
- snps,phyif_utmi_16_bits;
- snps,dis_u2_freeclk_exists_quirk;
- snps,dis_del_phy_power_chg_quirk;
- snps,xhci_slow_suspend_quirk;
+ snps,dis-u2-freeclk-exists-quirk;
+ snps,dis_u2_susphy_quirk;
+ snps,dis-del-phy-power-chg-quirk;
+ snps,xhci-slow-suspend-quirk;
status = "disabled";
};
};
#io-channel-cells = <1>;
clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
clock-names = "saradc", "apb_pclk";
+ resets = <&cru SRST_P_SARADC>;
+ reset-names = "saradc-apb";
status = "disabled";
};
};
/* These power domains are grouped by VD_LOGIC */
+ pd_edp@RK3399_PD_EDP {
+ reg = <RK3399_PD_EDP>;
+ clocks = <&cru PCLK_EDP_CTRL>;
+ };
pd_emmc@RK3399_PD_EMMC {
reg = <RK3399_PD_EMMC>;
clocks = <&cru ACLK_EMMC>;
};
pd_perihp@RK3399_PD_PERIHP {
reg = <RK3399_PD_PERIHP>;
+ #address-cells = <1>;
+ #size-cells = <0>;
clocks = <&cru ACLK_PERIHP>;
pm_qos = <&qos_perihp>,
<&qos_pcie>,
<&qos_usb_host0>,
<&qos_usb_host1>;
- };
- pd_sd@RK3399_PD_SD {
- reg = <RK3399_PD_SD>;
- clocks = <&cru HCLK_SDMMC>;
- pm_qos = <&qos_sd>;
+
+ pd_sd@RK3399_PD_SD {
+ reg = <RK3399_PD_SD>;
+ clocks = <&cru HCLK_SDMMC>,
+ <&cru SCLK_SDMMC>;
+ pm_qos = <&qos_sd>;
+ };
};
pd_sdioaudio@RK3399_PD_SDIOAUDIO {
reg = <RK3399_PD_SDIOAUDIO>;
pm_qos = <&qos_isp1_m0>,
<&qos_isp1_m1>;
};
+ pd_tcpc0@RK3399_PD_TCPC0 {
+ reg = <RK3399_PD_TCPD0>;
+ clocks = <&cru SCLK_UPHY0_TCPDCORE>,
+ <&cru SCLK_UPHY0_TCPDPHY_REF>;
+ };
+ pd_tcpc1@RK3399_PD_TCPC1 {
+ reg = <RK3399_PD_TCPD1>;
+ clocks = <&cru SCLK_UPHY1_TCPDCORE>,
+ <&cru SCLK_UPHY1_TCPDPHY_REF>;
+ };
pd_vo@RK3399_PD_VO {
reg = <RK3399_PD_VO>;
#address-cells = <1>;
mode-loader = <BOOT_LOADER>;
mode-normal = <BOOT_NORMAL>;
mode-recovery = <BOOT_RECOVERY>;
+ mode-ums = <BOOT_UMS>;
+ };
+
+ pmu_pvtm: pmu-pvtm {
+ compatible = "rockchip,rk3399-pmu-pvtm";
+ clocks = <&pmucru SCLK_PVTM_PMU>;
+ clock-names = "pmu";
+ status = "disabled";
};
};
status = "disabled";
};
+ pcie_phy: phy@e220 {
+ compatible = "rockchip,rk3399-pcie-phy";
+ #phy-cells = <0>;
+ rockchip,grf = <&grf>;
+ clocks = <&cru SCLK_PCIEPHY_REF>;
+ clock-names = "refclk";
+ resets = <&cru SRST_PCIEPHY>;
+ reset-names = "phy";
+ status = "disabled";
+ };
+
pcie0: pcie@f8000000 {
compatible = "rockchip,rk3399-pcie";
#address-cells = <3>;
#size-cells = <2>;
clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
- <&cru PCLK_PCIE>, <&cru SCLK_PCIEPHY_REF>;
- clock-names = "aclk_pcie", "aclk_perf_pcie",
- "hclk_pcie", "clk_pciephy_ref";
+ <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
+ clock-names = "aclk", "aclk-perf",
+ "hclk", "pm";
bus-range = <0x0 0x1>;
+ msi-map = <0x0 &its 0x0 0x1000>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "pcie-sys", "pcie-legacy", "pcie-client";
- ranges = < 0x82000000 0 0xfa000000 0x0 0xfa000000 0 0x600000
- 0x81000000 0 0xfa600000 0x0 0xfa600000 0 0x100000 >;
- reg = < 0x0 0xf8000000 0x0 0x2000000 >,
- < 0x0 0xfd000000 0x0 0x1000000 >;
- reg-name = "axi-base", "apb-base";
- resets = <&cru SRST_PCIEPHY>, <&cru SRST_PCIE_CORE>,
- <&cru SRST_PCIE_MGMT>, <&cru SRST_PCIE_MGMT_STICKY>,
- <&cru SRST_PCIE_PIPE>;
- reset-names = "phy-rst", "core-rst", "mgmt-rst",
- "mgmt-sticky-rst", "pipe-rst";
- rockchip,grf = <&grf>;
- pcie-conf = <0xe220>;
- pcie-status = <0xe2a4>;
- pcie-laneoff = <0xe214>;
- power-domains = <&power RK3399_PD_PERIHP>;
- msi-parent = <&its>;
+ interrupt-names = "sys", "legacy", "client";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
- interrupt-map = <0 0 0 1 &pcie0 1>,
- <0 0 0 2 &pcie0 2>,
- <0 0 0 3 &pcie0 3>,
- <0 0 0 4 &pcie0 4>;
+ interrupt-map = <0 0 0 1 &pcie0_intc 0>,
+ <0 0 0 2 &pcie0_intc 1>,
+ <0 0 0 3 &pcie0_intc 2>,
+ <0 0 0 4 &pcie0_intc 3>;
+ phys = <&pcie_phy>;
+ phy-names = "pcie-phy";
+ ranges = <0x82000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
+ 0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
+ reg = <0x0 0xf8000000 0x0 0x2000000>,
+ <0x0 0xfd000000 0x0 0x1000000>;
+ reg-names = "axi-base", "apb-base";
+ resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
+ <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,
+ <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>,
+ <&cru SRST_A_PCIE>;
+ reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
+ "pm", "pclk", "aclk";
status = "disabled";
- pcie_intc: interrupt-controller {
+ pcie0_intc: interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
status = "disabled";
};
+ dfi: dfi@ff630000 {
+ reg = <0x00 0xff630000 0x00 0x4000>;
+ compatible = "rockchip,rk3399-dfi";
+ rockchip,pmu = <&pmugrf>;
+ clocks = <&cru PCLK_DDR_MON>;
+ clock-names = "pclk_ddr_mon";
+ status = "disabled";
+ };
+
+ dmc: dmc {
+ compatible = "rockchip,rk3399-dmc";
+ devfreq-events = <&dfi>;
+ interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru SCLK_DDRCLK>;
+ clock-names = "dmc_clk";
+ ddr_timing = <&ddr_timing>;
+ operating-points-v2 = <&dmc_opp_table>;
+ status = "disabled";
+ };
+
+ dmc_opp_table: dmc_opp_table {
+ compatible = "operating-points-v2";
+
+ opp00 {
+ opp-hz = /bits/ 64 <666000000>;
+ opp-microvolt = <900000>;
+ };
+ };
+
rga: rga@ff680000 {
compatible = "rockchip,rk3399-rga";
reg = <0x0 0xff680000 0x0 0x10000>;
status = "disabled";
};
+ efuse0: efuse@ff690000 {
+ compatible = "rockchip,rk3399-efuse";
+ reg = <0x0 0xff690000 0x0 0x80>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clocks = <&cru PCLK_EFUSE1024NS>;
+ clock-names = "pclk_efuse";
+
+ /* Data cells */
+ cpul_leakage: cpul-leakage {
+ reg = <0x1a 0x1>;
+ };
+ cpub_leakage: cpub-leakage {
+ reg = <0x17 0x1>;
+ };
+ gpu_leakage: gpu-leakage {
+ reg = <0x18 0x1>;
+ };
+ center_leakage: center-leakage {
+ reg = <0x19 0x1>;
+ };
+ logic_leakage: logic-leakage {
+ reg = <0x1b 0x1>;
+ };
+ wafer_info: wafer-info {
+ reg = <0x1c 0x1>;
+ };
+ };
+
pmucru: pmu-clock-controller@ff750000 {
compatible = "rockchip,rk3399-pmucru";
reg = <0x0 0xff750000 0x0 0x1000>;
<&cru ACLK_VOP1>, <&cru HCLK_VOP1>,
<&cru ARMCLKL>, <&cru ARMCLKB>,
<&cru PLL_GPLL>, <&cru PLL_CPLL>,
- <&cru PLL_NPLL>,
+ <&cru ACLK_GPU>, <&cru PLL_NPLL>,
<&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
<&cru PCLK_PERIHP>,
<&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
<400000000>, <200000000>,
<816000000>, <816000000>,
<594000000>, <800000000>,
- <1000000000>,
+ <200000000>, <1000000000>,
<150000000>, <75000000>,
<37500000>,
<100000000>, <100000000>,
#address-cells = <1>;
#size-cells = <1>;
+ emmc_phy: phy@f780 {
+ compatible = "rockchip,rk3399-emmc-phy";
+ reg = <0xf780 0x24>;
+ clocks = <&sdhci>;
+ clock-names = "emmcclk";
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
u2phy0: usb2-phy@e450 {
compatible = "rockchip,rk3399-usb2phy";
reg = <0xe450 0x10>;
u2phy1_otg: otg-port {
#phy-cells = <0>;
- interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "otg-bvalid", "otg-id",
"linestate";
status = "disabled";
status = "disabled";
};
};
+
+ pvtm: pvtm {
+ compatible = "rockchip,rk3399-pvtm";
+ clocks = <&cru SCLK_PVTM_CORE_L>,
+ <&cru SCLK_PVTM_CORE_B>,
+ <&cru SCLK_PVTM_GPU>,
+ <&cru SCLK_PVTM_DDR>;
+ clock-names = "core_l", "core_b", "gpu", "ddr";
+ status = "disabled";
+ };
};
tcphy0: phy@ff7c0000 {
compatible = "rockchip,rk3399-typec-phy";
reg = <0x0 0xff7c0000 0x0 0x40000>;
rockchip,grf = <&grf>;
- #phy-cells = <0>;
+ #phy-cells = <1>;
clocks = <&cru SCLK_UPHY0_TCPDCORE>,
<&cru SCLK_UPHY0_TCPDPHY_REF>;
clock-names = "tcpdcore", "tcpdphy-ref";
+ assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
+ assigned-clock-rates = <50000000>;
+ power-domains = <&power RK3399_PD_TCPD0>;
resets = <&cru SRST_UPHY0>,
<&cru SRST_UPHY0_PIPE_L00>,
<&cru SRST_P_UPHY0_TCPHY>;
reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
rockchip,typec-conn-dir = <0xe580 0 16>;
rockchip,usb3tousb2-en = <0xe580 3 19>;
+ rockchip,usb3-host-disable = <0x2434 0 16>;
+ rockchip,usb3-host-port = <0x2434 12 28>;
rockchip,external-psm = <0xe588 14 30>;
rockchip,pipe-status = <0xe5c0 0 0>;
rockchip,uphy-dp-sel = <0x6268 19 19>;
status = "disabled";
+
+ tcphy0_dp: dp-port {
+ #phy-cells = <0>;
+ };
+
+ tcphy0_usb3: usb3-port {
+ #phy-cells = <0>;
+ };
};
tcphy1: phy@ff800000 {
compatible = "rockchip,rk3399-typec-phy";
reg = <0x0 0xff800000 0x0 0x40000>;
rockchip,grf = <&grf>;
- #phy-cells = <0>;
+ #phy-cells = <1>;
clocks = <&cru SCLK_UPHY1_TCPDCORE>,
<&cru SCLK_UPHY1_TCPDPHY_REF>;
clock-names = "tcpdcore", "tcpdphy-ref";
+ assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
+ assigned-clock-rates = <50000000>;
+ power-domains = <&power RK3399_PD_TCPD1>;
resets = <&cru SRST_UPHY1>,
<&cru SRST_UPHY1_PIPE_L00>,
<&cru SRST_P_UPHY1_TCPHY>;
reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
rockchip,typec-conn-dir = <0xe58c 0 16>;
rockchip,usb3tousb2-en = <0xe58c 3 19>;
+ rockchip,usb3-host-disable = <0x2444 0 16>;
+ rockchip,usb3-host-port = <0x2444 12 28>;
rockchip,external-psm = <0xe594 14 30>;
rockchip,pipe-status = <0xe5c0 16 16>;
rockchip,uphy-dp-sel = <0x6268 3 19>;
status = "disabled";
+
+ tcphy1_dp: dp-port {
+ #phy-cells = <0>;
+ };
+
+ tcphy1_usb3: usb3-port {
+ #phy-cells = <0>;
+ };
};
- watchdog@ff840000 {
+ watchdog@ff848000 {
compatible = "snps,dw-wdt";
- reg = <0x0 0xff840000 0x0 0x100>;
+ reg = <0x0 0xff848000 0x0 0x100>;
clocks = <&cru PCLK_WDT>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
};
clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
pinctrl-names = "default";
pinctrl-0 = <&spdif_bus>;
+ power-domains = <&power RK3399_PD_SDIOAUDIO>;
status = "disabled";
};
clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
pinctrl-names = "default";
pinctrl-0 = <&i2s0_8ch_bus>;
+ power-domains = <&power RK3399_PD_SDIOAUDIO>;
status = "disabled";
};
clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
pinctrl-names = "default";
pinctrl-0 = <&i2s1_2ch_bus>;
+ power-domains = <&power RK3399_PD_SDIOAUDIO>;
status = "disabled";
};
dma-names = "tx", "rx";
clock-names = "i2s_clk", "i2s_hclk";
clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
+ power-domains = <&power RK3399_PD_SDIOAUDIO>;
status = "disabled";
};
};
};
+ vop1_pwm: voppwm@ff8f01a0 {
+ compatible = "rockchip,vop-pwm";
+ reg = <0x0 0xff8f01a0 0x0 0x10>;
+ #pwm-cells = <3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vop1_pwm_pin>;
+ clocks = <&cru SCLK_VOP1_PWM>;
+ clock-names = "pwm";
+ status = "disabled";
+ };
+
vopl_mmu: iommu@ff8f3f00 {
compatible = "rockchip,iommu";
reg = <0x0 0xff8f3f00 0x0 0x100>;
};
};
+ vop0_pwm: voppwm@ff9001a0 {
+ compatible = "rockchip,vop-pwm";
+ reg = <0x0 0xff9001a0 0x0 0x10>;
+ #pwm-cells = <3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vop0_pwm_pin>;
+ clocks = <&cru SCLK_VOP0_PWM>;
+ clock-names = "pwm";
+ status = "disabled";
+ };
+
vopb_mmu: iommu@ff903f00 {
compatible = "rockchip,iommu";
reg = <0x0 0xff903f00 0x0 0x100>;
reg-io-width = <4>;
rockchip,grf = <&grf>;
power-domains = <&power RK3399_PD_HDCP>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_i2c_xfer>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, <&cru SCLK_HDMI_SFR>, <&cru PCLK_EDP_CTRL>;
clock-names = "iahb", "isfr", "vpll", "grf";
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
clock-names = "dp", "pclk";
+ power-domains = <&power RK3399_PD_EDP>;
resets = <&cru SRST_P_EDP_CTRL>;
reset-names = "dp";
rockchip,grf = <&grf>;
drive-strength = <13>;
};
+ pcfg_output_high: pcfg-output-high {
+ output-high;
+ };
+
+ pcfg_output_low: pcfg-output-low {
+ output-low;
+ };
+
+ pcfg_input: pcfg-input {
+ input-enable;
+ };
+
emmc {
emmc_pwr: emmc-pwr {
rockchip,pins =
projects / firefly-linux-kernel-4.4.55.git / blobdiff