serial1 = &uart1;
serial2 = &uart2;
serial3 = &uart3;
+ serial4 = &uart4;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
};
cpus {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x0>;
-
+ enable-method = "psci";
#cooling-cells = <2>; /* min followed by max */
clocks = <&cru ARMCLKL>;
operating-points-v2 = <&cluster0_opp>;
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x1>;
+ enable-method = "psci";
clocks = <&cru ARMCLKL>;
operating-points-v2 = <&cluster0_opp>;
};
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x2>;
+ enable-method = "psci";
clocks = <&cru ARMCLKL>;
operating-points-v2 = <&cluster0_opp>;
};
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x3>;
+ enable-method = "psci";
clocks = <&cru ARMCLKL>;
operating-points-v2 = <&cluster0_opp>;
};
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x0 0x100>;
-
+ enable-method = "psci";
#cooling-cells = <2>; /* min followed by max */
clocks = <&cru ARMCLKB>;
operating-points-v2 = <&cluster1_opp>;
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x0 0x101>;
+ enable-method = "psci";
clocks = <&cru ARMCLKB>;
operating-points-v2 = <&cluster1_opp>;
};
opp00 {
opp-hz = /bits/ 64 <408000000>;
- opp-microvolt = <1000000>;
+ opp-microvolt = <900000>;
clock-latency-ns = <40000>;
};
opp01 {
opp-hz = /bits/ 64 <600000000>;
- opp-microvolt = <1000000>;
+ opp-microvolt = <900000>;
};
opp02 {
opp-hz = /bits/ 64 <816000000>;
- opp-microvolt = <1000000>;
+ opp-microvolt = <900000>;
};
opp03 {
opp-hz = /bits/ 64 <1008000000>;
- opp-microvolt = <1000000>;
+ opp-microvolt = <900000>;
};
};
opp00 {
opp-hz = /bits/ 64 <408000000>;
- opp-microvolt = <1000000>;
+ opp-microvolt = <900000>;
clock-latency-ns = <40000>;
};
opp01 {
opp-hz = /bits/ 64 <600000000>;
- opp-microvolt = <1000000>;
+ opp-microvolt = <900000>;
};
opp02 {
opp-hz = /bits/ 64 <816000000>;
- opp-microvolt = <1000000>;
+ opp-microvolt = <900000>;
};
opp03 {
opp-hz = /bits/ 64 <1008000000>;
- opp-microvolt = <1000000>;
+ opp-microvolt = <900000>;
};
opp04 {
opp-hz = /bits/ 64 <1200000000>;
- opp-microvolt = <1000000>;
+ opp-microvolt = <900000>;
};
};
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
+ pmu_a53 {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-affinity = <&cpu_l0>,
+ <&cpu_l1>,
+ <&cpu_l2>,
+ <&cpu_l3>;
+ };
+
+ pmu_a72 {
+ compatible = "arm,cortex-a72-pmu", "arm,cortex-a57-pmu";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-affinity = <&cpu_b0>,
+ <&cpu_b1>;
+ };
+
xin24m: xin24m {
compatible = "fixed-clock";
#clock-cells = <0>;
};
};
+ gmac: eth@fe300000 {
+ compatible = "rockchip,rk3399-gmac";
+ reg = <0x0 0xfe300000 0x0 0x10000>;
+ rockchip,grf = <&grf>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
+ <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
+ <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
+ <&cru PCLK_GMAC>;
+ clock-names = "stmmaceth", "mac_clk_rx",
+ "mac_clk_tx", "clk_mac_ref",
+ "clk_mac_refout", "aclk_mac",
+ "pclk_mac";
+ resets = <&cru SRST_A_GMAC>;
+ reset-names = "stmmaceth";
+ status = "disabled";
+ };
+
emmc_phy: phy {
compatible = "rockchip,rk3399-emmc-phy";
reg-offset = <0xf780>;
status = "disabled";
};
+ usb2phy {
+ compatible = "rockchip,rk3399-usb-phy";
+ rockchip,grf = <&grf>;
+ vbus_drv-gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usb2phy0: usb2-phy0 {
+ #phy-cells = <0>;
+ #clock-cells = <0>;
+ reg = <0xe458>;
+ };
+
+ usb2phy1: usb2-phy1 {
+ #phy-cells = <0>;
+ #clock-cells = <0>;
+ reg = <0xe468>;
+ };
+ };
+
usb_host0_echi: usb@fe380000 {
compatible = "generic-ehci";
reg = <0x0 0xfe380000 0x0 0x20000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru HCLK_HOST0>;
- clock-names = "hclk_host0";
+ clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
+ clock-names = "hclk_host0", "hclk_host0_arb";
+ phys = <&usb2phy0>;
+ phy-names = "usb2_phy0";
status = "disabled";
};
compatible = "generic-ohci";
reg = <0x0 0xfe3a0000 0x0 0x20000>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru HCLK_HOST0>;
- clock-names = "hclk_host0";
+ clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
+ clock-names = "hclk_host0", "hclk_host0_arb";
status = "disabled";
};
compatible = "generic-ehci";
reg = <0x0 0xfe3c0000 0x0 0x20000>;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru HCLK_HOST1>;
- clock-names = "hclk_host1";
+ clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
+ clock-names = "hclk_host1", "hclk_host1_arb";
+ phys = <&usb2phy1>;
+ phy-names = "usb2_phy1";
status = "disabled";
};
compatible = "generic-ohci";
reg = <0x0 0xfe3e0000 0x0 0x20000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru HCLK_HOST1>;
- clock-names = "hclk_host1";
+ clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
+ clock-names = "hclk_host1", "hclk_host1_arb";
+ status = "disabled";
+ };
+
+ usbdrd3_0: usb@fe800000 {
+ compatible = "rockchip,dwc3";
+ clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
+ <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
+ <&cru ACLK_USB3>, <&cru ACLK_USB3_NOC>,
+ <&cru ACLK_USB3_GRF>;
+ clock-names = "clk_usb3otg0_ref", "clk_usb3otg0_suspend",
+ "aclk_usb3otg0", "aclk_usb3_rksoc_axi_perf",
+ "aclk_usb3", "aclk_usb3_noc",
+ "aclk_usb3_grf";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+ usbdrd_dwc3_0: dwc3 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0xfe800000 0x0 0x100000>;
+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ dr_mode = "otg";
+ tx-fifo-resize;
+ snps,dis_enblslpm_quirk;
+ snps,phyif_utmi_16_bits;
+ snps,dis_u2_freeclk_exists_quirk;
+ snps,dis_del_phy_power_chg_quirk;
+ status = "disabled";
+ };
+ };
+
+ usbdrd3_1: usb@fe900000 {
+ compatible = "rockchip,dwc3";
+ clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
+ <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
+ <&cru ACLK_USB3>, <&cru ACLK_USB3_NOC>,
+ <&cru ACLK_USB3_GRF>;
+ clock-names = "clk_usb3otg1_ref", "clk_usb3otg1_suspend",
+ "aclk_usb3otg1", "aclk_usb3_rksoc_axi_perf",
+ "aclk_usb3", "aclk_usb3_noc",
+ "aclk_usb3_grf";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
status = "disabled";
+ usbdrd_dwc3_1: dwc3 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0xfe900000 0x0 0x100000>;
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ dr_mode = "otg";
+ tx-fifo-resize;
+ snps,dis_enblslpm_quirk;
+ snps,phyif_utmi_16_bits;
+ snps,dis_u2_freeclk_exists_quirk;
+ snps,dis_del_phy_power_chg_quirk;
+ status = "disabled";
+ };
};
gic: interrupt-controller@fee00000 {
};
i2c0: i2c@ff3c0000 {
- compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
+ compatible = "rockchip,rk3399-i2c";
reg = <0x0 0xff3c0000 0x0 0x1000>;
- clocks = <&cru PCLK_I2C0_PMU>, <&cru SCLK_I2C0_PMU>;
- clock-names = "i2c", "i2c_sclk";
+ clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
+ clock-names = "i2c", "pclk";
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&i2c0_xfer>;
};
i2c1: i2c@ff110000 {
- compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
+ compatible = "rockchip,rk3399-i2c";
reg = <0x0 0xff110000 0x0 0x1000>;
- clocks = <&cru PCLK_I2C1>, <&cru SCLK_I2C1>;
- clock-names = "i2c", "i2c_sclk";
+ clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
+ clock-names = "i2c", "pclk";
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&i2c1_xfer>;
};
i2c2: i2c@ff120000 {
- compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
+ compatible = "rockchip,rk3399-i2c";
reg = <0x0 0xff120000 0x0 0x1000>;
- clocks = <&cru PCLK_I2C2>, <&cru SCLK_I2C2>;
- clock-names = "i2c", "i2c_sclk";
+ clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
+ clock-names = "i2c", "pclk";
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&i2c2_xfer>;
};
i2c3: i2c@ff130000 {
- compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
+ compatible = "rockchip,rk3399-i2c";
reg = <0x0 0xff130000 0x0 0x1000>;
- clocks = <&cru PCLK_I2C3>, <&cru SCLK_I2C3>;
- clock-names = "i2c", "i2c_sclk";
+ clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
+ clock-names = "i2c", "pclk";
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&i2c3_xfer>;
};
i2c5: i2c@ff140000 {
- compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
+ compatible = "rockchip,rk3399-i2c";
reg = <0x0 0xff140000 0x0 0x1000>;
- clocks = <&cru PCLK_I2C5>, <&cru SCLK_I2C5>;
- clock-names = "i2c", "i2c_sclk";
+ clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
+ clock-names = "i2c", "pclk";
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&i2c5_xfer>;
};
i2c6: i2c@ff150000 {
- compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
+ compatible = "rockchip,rk3399-i2c";
reg = <0x0 0xff150000 0x0 0x1000>;
- clocks = <&cru PCLK_I2C6>, <&cru SCLK_I2C6>;
- clock-names = "i2c", "i2c_sclk";
+ clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
+ clock-names = "i2c", "pclk";
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&i2c6_xfer>;
};
i2c7: i2c@ff160000 {
- compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
+ compatible = "rockchip,rk3399-i2c";
reg = <0x0 0xff160000 0x0 0x1000>;
- clocks = <&cru PCLK_I2C7>, <&cru SCLK_I2C7>;
- clock-names = "i2c", "i2c_sclk";
+ clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
+ clock-names = "i2c", "pclk";
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&i2c7_xfer>;
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
status = "disabled";
};
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_xfer>;
status = "disabled";
};
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2c_xfer>;
status = "disabled";
};
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
status = "disabled";
};
spi3: spi@ff350000 {
compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
reg = <0x0 0xff350000 0x0 0x1000>;
- clocks = <&cru SCLK_SPI3_PMU>, <&cru PCLK_SPI3_PMU>;
+ clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
clock-names = "spiclk", "apb_pclk";
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
uart4: serial@ff370000 {
compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
reg = <0x0 0xff370000 0x0 0x100>;
- clocks = <&cru SCLK_UART4_PMU>, <&cru PCLK_UART4_PMU>;
+ clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart4_xfer>;
status = "disabled";
};
i2c4: i2c@ff3d0000 {
- compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
+ compatible = "rockchip,rk3399-i2c";
reg = <0x0 0xff3d0000 0x0 0x1000>;
- clocks = <&cru PCLK_I2C4_PMU>, <&cru SCLK_I2C4_PMU>;
- clock-names = "i2c", "i2c_sclk";
+ clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
+ clock-names = "i2c", "pclk";
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&i2c4_xfer>;
};
i2c8: i2c@ff3e0000 {
- compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
+ compatible = "rockchip,rk3399-i2c";
reg = <0x0 0xff3e0000 0x0 0x1000>;
- clocks = <&cru PCLK_I2C8_PMU>, <&cru SCLK_I2C8_PMU>;
- clock-names = "i2c", "i2c_sclk";
+ clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
+ clock-names = "i2c", "pclk";
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&i2c8_xfer>;
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-0 = <&pwm0_pin>;
- clocks = <&cru PCLK_RKPWM_PMU>;
+ clocks = <&pmucru PCLK_RKPWM_PMU>;
clock-names = "pwm";
status = "disabled";
};
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-0 = <&pwm1_pin>;
- clocks = <&cru PCLK_RKPWM_PMU>;
+ clocks = <&pmucru PCLK_RKPWM_PMU>;
clock-names = "pwm";
status = "disabled";
};
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-0 = <&pwm2_pin>;
- clocks = <&cru PCLK_RKPWM_PMU>;
+ clocks = <&pmucru PCLK_RKPWM_PMU>;
clock-names = "pwm";
status = "disabled";
};
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-0 = <&pwm3a_pin>;
- clocks = <&cru PCLK_RKPWM_PMU>;
+ clocks = <&pmucru PCLK_RKPWM_PMU>;
clock-names = "pwm";
status = "disabled";
};
rockchip,grf = <&pmugrf>;
#clock-cells = <1>;
#reset-cells = <1>;
+ assigned-clocks = <&pmucru PLL_PPLL>;
+ assigned-clock-rates = <676000000>;
};
cru: clock-controller@ff760000 {
rockchip,grf = <&grf>;
#clock-cells = <1>;
#reset-cells = <1>;
+ assigned-clocks =
+ <&cru ARMCLKL>, <&cru ARMCLKB>,
+ <&cru PLL_GPLL>, <&cru PLL_CPLL>,
+ <&cru PLL_NPLL>,
+ <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
+ <&cru PCLK_PERIHP>,
+ <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
+ <&cru PCLK_PERILP0>,
+ <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
+ assigned-clock-rates =
+ <816000000>, <1008000000>,
+ <594000000>, <800000000>,
+ <1000000000>,
+ <150000000>, <75000000>,
+ <37500000>,
+ <100000000>, <100000000>,
+ <50000000>,
+ <100000000>, <50000000>;
};
grf: syscon@ff770000 {
gpio0: gpio0@ff720000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff720000 0x0 0x100>;
- clocks = <&xin24m>;
+ clocks = <&pmucru PCLK_GPIO0_PMU>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
gpio1: gpio1@ff730000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff730000 0x0 0x100>;
- clocks = <&xin24m>;
+ clocks = <&pmucru PCLK_GPIO1_PMU>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
gpio2: gpio2@ff780000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff780000 0x0 0x100>;
- clocks = <&xin24m>;
+ clocks = <&cru PCLK_GPIO2>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
gpio3: gpio3@ff788000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff788000 0x0 0x100>;
- clocks = <&xin24m>;
+ clocks = <&cru PCLK_GPIO3>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
gpio4: gpio4@ff790000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff790000 0x0 0x100>;
- clocks = <&xin24m>;
+ clocks = <&cru PCLK_GPIO4>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
gmac {
rgmii_pins: rgmii-pins {
rockchip,pins =
- <3 11 RK_FUNC_1 &pcfg_pull_none>,
- <3 13 RK_FUNC_1 &pcfg_pull_none>,
- <3 8 RK_FUNC_1 &pcfg_pull_none>,
- <3 4 RK_FUNC_1 &pcfg_pull_none_12ma>,
- <3 5 RK_FUNC_1 &pcfg_pull_none_12ma>,
- <3 0 RK_FUNC_1 &pcfg_pull_none_12ma>,
- <3 1 RK_FUNC_1 &pcfg_pull_none_12ma>,
+ /* mac_txclk */
<3 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
+ /* mac_rxclk */
+ <3 14 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_mdio */
+ <3 13 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_txen */
<3 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
- <3 6 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_clk */
+ <3 11 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_rxdv */
+ <3 9 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_mdc */
+ <3 8 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_rxd1 */
<3 7 RK_FUNC_1 &pcfg_pull_none>,
- <3 2 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_rxd0 */
+ <3 6 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_txd1 */
+ <3 5 RK_FUNC_1 &pcfg_pull_none_12ma>,
+ /* mac_txd0 */
+ <3 4 RK_FUNC_1 &pcfg_pull_none_12ma>,
+ /* mac_rxd3 */
<3 3 RK_FUNC_1 &pcfg_pull_none>,
- <3 14 RK_FUNC_1 &pcfg_pull_none>,
- <3 9 RK_FUNC_1 &pcfg_pull_none>;
+ /* mac_rxd2 */
+ <3 2 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_txd3 */
+ <3 1 RK_FUNC_1 &pcfg_pull_none_12ma>,
+ /* mac_txd2 */
+ <3 0 RK_FUNC_1 &pcfg_pull_none_12ma>;
};
rmii_pins: rmii-pins {
rockchip,pins =
- <3 11 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_mdio */
<3 13 RK_FUNC_1 &pcfg_pull_none>,
- <3 8 RK_FUNC_1 &pcfg_pull_none>,
- <3 4 RK_FUNC_1 &pcfg_pull_none_12ma>,
- <3 5 RK_FUNC_1 &pcfg_pull_none_12ma>,
+ /* mac_txen */
<3 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
- <3 6 RK_FUNC_1 &pcfg_pull_none>,
- <3 7 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_clk */
+ <3 11 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_rxer */
+ <3 10 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_rxdv */
<3 9 RK_FUNC_1 &pcfg_pull_none>,
- <3 10 RK_FUNC_1 &pcfg_pull_none>;
+ /* mac_mdc */
+ <3 8 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_rxd1 */
+ <3 7 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_rxd0 */
+ <3 6 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_txd1 */
+ <3 5 RK_FUNC_1 &pcfg_pull_none_12ma>,
+ /* mac_txd0 */
+ <3 4 RK_FUNC_1 &pcfg_pull_none_12ma>;
};
};
projects / firefly-linux-kernel-4.4.55.git / blobdiff