ARM64: dts: rk3399: add powerdomain for vop
[firefly-linux-kernel-4.4.55.git] / arch / arm64 / boot / dts / rockchip / rk3399.dtsi
index 9c14ed2784f153592a467252465e645b93b718b4..6aa9f3bb5223df757311d4aa03106c7b3d03fa6c 100644 (file)
                        clocks = <&cru ARMCLKL>;
                        cpu-idle-states = <&cpu_sleep>;
                        operating-points-v2 = <&cluster0_opp>;
+                       sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
                };
 
                cpu_l1: cpu@1 {
                        clocks = <&cru ARMCLKL>;
                        cpu-idle-states = <&cpu_sleep>;
                        operating-points-v2 = <&cluster0_opp>;
+                       sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
                };
 
                cpu_l2: cpu@2 {
                        clocks = <&cru ARMCLKL>;
                        cpu-idle-states = <&cpu_sleep>;
                        operating-points-v2 = <&cluster0_opp>;
+                       sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
                };
 
                cpu_l3: cpu@3 {
                        clocks = <&cru ARMCLKL>;
                        cpu-idle-states = <&cpu_sleep>;
                        operating-points-v2 = <&cluster0_opp>;
+                       sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
                };
 
                cpu_b0: cpu@100 {
                        clocks = <&cru ARMCLKB>;
                        cpu-idle-states = <&cpu_sleep>;
                        operating-points-v2 = <&cluster1_opp>;
+                       sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
                };
 
                cpu_b1: cpu@101 {
                        clocks = <&cru ARMCLKB>;
                        cpu-idle-states = <&cpu_sleep>;
                        operating-points-v2 = <&cluster1_opp>;
+                       sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
                };
 
                idle-states {
                                min-residency-us = <1150>;
                        };
                };
+
+               /include/ "rk3399-sched-energy.dtsi"
+
        };
 
        cluster0_opp: opp_table0 {
                        #dma-cells = <1>;
                        clocks = <&cru ACLK_DMAC0_PERILP>;
                        clock-names = "apb_pclk";
+                       peripherals-req-type-burst;
                };
 
                dmac_peri: dma-controller@ff6e0000 {
                        #dma-cells = <1>;
                        clocks = <&cru ACLK_DMAC1_PERILP>;
                        clock-names = "apb_pclk";
+                       peripherals-req-type-burst;
                };
        };
 
                #size-cells = <2>;
                ranges;
                status = "disabled";
-               usbdrd_dwc3_0: dwc3 {
+               usbdrd_dwc3_0: dwc3@fe800000 {
                        compatible = "snps,dwc3";
                        reg = <0x0 0xfe800000 0x0 0x100000>;
                        interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
                        dr_mode = "otg";
-                       tx-fifo-resize;
                        snps,dis_enblslpm_quirk;
                        snps,phyif_utmi_16_bits;
                        snps,dis_u2_freeclk_exists_quirk;
                #size-cells = <2>;
                ranges;
                status = "disabled";
-               usbdrd_dwc3_1: dwc3 {
+               usbdrd_dwc3_1: dwc3@fe900000 {
                        compatible = "snps,dwc3";
                        reg = <0x0 0xfe900000 0x0 0x100000>;
                        interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
                        dr_mode = "otg";
-                       tx-fifo-resize;
                        snps,dis_enblslpm_quirk;
                        snps,phyif_utmi_16_bits;
                        snps,dis_u2_freeclk_exists_quirk;
                status = "disabled";
        };
 
-       qos_gpu: qos_gpu@0xffae0000 {
-               compatible ="syscon";
+       qos_gpu: qos_gpu@ffae0000 {
+               compatible = "syscon";
                reg = <0x0 0xffae0000 0x0 0x20>;
        };
-       qos_video_m0: qos_video_m0@0xffab8000 {
-               compatible ="syscon";
+       qos_video_m0: qos_video_m0@ffab8000 {
+               compatible = "syscon";
                reg = <0x0 0xffab8000 0x0 0x20>;
        };
-       qos_video_m1_r: qos_video_m1_r@0xffac0000 {
-               compatible ="syscon";
+       qos_video_m1_r: qos_video_m1_r@ffac0000 {
+               compatible = "syscon";
                reg = <0x0 0xffac0000 0x0 0x20>;
        };
-       qos_video_m1_w: qos_video_m1_w@0xffac0080 {
-               compatible ="syscon";
+       qos_video_m1_w: qos_video_m1_w@ffac0080 {
+               compatible = "syscon";
                reg = <0x0 0xffac0080 0x0 0x20>;
        };
-       qos_rga_r: qos_rga_r@0xffab0000 {
-               compatible ="syscon";
+       qos_rga_r: qos_rga_r@ffab0000 {
+               compatible = "syscon";
                reg = <0x0 0xffab0000 0x0 0x20>;
        };
-       qos_rga_w: qos_rga_w@0xffab0080 {
-               compatible ="syscon";
-               reg = <0x0 0xffab0000 0x0 0x20>;
+       qos_rga_w: qos_rga_w@ffab0080 {
+               compatible = "syscon";
+               reg = <0x0 0xffab0080 0x0 0x20>;
        };
-       qos_iep: qos_iep@0xffa98000 {
-               compatible ="syscon";
+       qos_iep: qos_iep@ffa98000 {
+               compatible = "syscon";
                reg = <0x0 0xffa98000 0x0 0x20>;
        };
-       qos_vop_big_r: qos_vop_big_r@0xffac8000 {
-               compatible ="syscon";
+       qos_vop_big_r: qos_vop_big_r@ffac8000 {
+               compatible = "syscon";
                reg = <0x0 0xffac8000 0x0 0x20>;
        };
-       qos_vop_big_w: qos_vop_big_w@0xffac8080 {
-               compatible ="syscon";
+       qos_vop_big_w: qos_vop_big_w@ffac8080 {
+               compatible = "syscon";
                reg = <0x0 0xffac8080 0x0 0x20>;
        };
-       qos_vop_little: qos_vop_little@0xffad0000 {
-               compatible ="syscon";
+       qos_vop_little: qos_vop_little@ffad0000 {
+               compatible = "syscon";
                reg = <0x0 0xffad0000 0x0 0x20>;
        };
-       qos_isp0_m0: qos_isp0_m0@0xffaa0000 {
-               compatible ="syscon";
+       qos_isp0_m0: qos_isp0_m0@ffaa0000 {
+               compatible = "syscon";
                reg = <0x0 0xffaa0000 0x0 0x20>;
        };
-       qos_isp0_m1: qos_isp0_m1@0xffaa0080 {
-               compatible ="syscon";
+       qos_isp0_m1: qos_isp0_m1@ffaa0080 {
+               compatible = "syscon";
                reg = <0x0 0xffaa0080 0x0 0x20>;
        };
-       qos_isp1_m0: qos_isp1_m0@0xffaa8000 {
-               compatible ="syscon";
+       qos_isp1_m0: qos_isp1_m0@ffaa8000 {
+               compatible = "syscon";
                reg = <0x0 0xffaa8000 0x0 0x20>;
        };
-       qos_isp1_m1: qos_isp1_m1@0xffaa8080 {
-               compatible ="syscon";
+       qos_isp1_m1: qos_isp1_m1@ffaa8080 {
+               compatible = "syscon";
                reg = <0x0 0xffaa8080 0x0 0x20>;
        };
-       qos_hdcp: qos_hdcp@0xffa90000 {
-               compatible ="syscon";
+       qos_hdcp: qos_hdcp@ffa90000 {
+               compatible = "syscon";
                reg = <0x0 0xffa90000 0x0 0x20>;
        };
 
 
                        pd_vdu {
                                reg = <RK3399_PD_VDU>;
+                               clocks = <&cru ACLK_VDU>,
+                                        <&cru HCLK_VDU>;
                                pm_qos = <&qos_video_m1_r>,
                                         <&qos_video_m1_w>;
                        };
                        pd_vcodec {
                                reg = <RK3399_PD_VCODEC>;
+                               clocks = <&cru ACLK_VCODEC>,
+                                        <&cru HCLK_VCODEC>;
                                pm_qos = <&qos_video_m0>;
                        };
                        pd_iep {
                                reg = <RK3399_PD_IEP>;
+                               clocks = <&cru ACLK_IEP>,
+                                        <&cru HCLK_IEP>;
                                pm_qos = <&qos_iep>;
                        };
                        pd_rga {
                                reg = <RK3399_PD_RGA>;
+                               clocks = <&cru ACLK_RGA>,
+                                        <&cru HCLK_RGA>;
                                pm_qos = <&qos_rga_r>,
                                         <&qos_rga_w>;
                        };
 
                                pd_isp0 {
                                        reg = <RK3399_PD_ISP0>;
+                                       clocks = <&cru ACLK_ISP0>,
+                                                <&cru HCLK_ISP0>;
                                        pm_qos = <&qos_isp0_m0>,
                                                 <&qos_isp0_m1>;
                                };
                                pd_isp1 {
                                        reg = <RK3399_PD_ISP1>;
+                                       clocks = <&cru ACLK_ISP1>,
+                                                <&cru HCLK_ISP1>;
                                        pm_qos = <&qos_isp1_m0>,
                                                 <&qos_isp1_m1>;
                                };
                                pd_hdcp {
                                        reg = <RK3399_PD_HDCP>;
+                                       clocks = <&cru ACLK_HDCP>,
+                                                <&cru HCLK_HDCP>,
+                                                <&cru PCLK_HDCP>;
                                        pm_qos = <&qos_hdcp>;
                                };
                                pd_vo {
 
                                        pd_vopb {
                                                reg = <RK3399_PD_VOPB>;
+                                               clocks = <&cru ACLK_VOP0>,
+                                                        <&cru HCLK_VOP0>;
                                                pm_qos = <&qos_vop_big_r>,
                                                         <&qos_vop_big_w>;
                                        };
                                        pd_vopl {
                                                reg = <RK3399_PD_VOPL>;
+                                               clocks = <&cru ACLK_VOP1>,
+                                                        <&cru HCLK_VOP1>;
                                                pm_qos = <&qos_vop_little>;
                                        };
                                };
                        };
                        pd_gpu {
                                reg = <RK3399_PD_GPU>;
+                               clocks = <&cru ACLK_GPU>;
                                pm_qos = <&qos_gpu>;
                        };
                };
                clock-names = "clk_mali";
                #cooling-cells = <2>; /* min followed by max */
                operating-points-v2 = <&gpu_opp_table>;
-
+               power-domains = <&power RK3399_PD_GPU>;
+               power-off-delay-ms = <200>;
                status = "disabled";
 
                power_model {
                clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
                resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
                reset-names = "axi", "ahb", "dclk";
+               power-domains = <&power RK3399_PD_VOPL>;
                iommus = <&vopl_mmu>;
                status = "disabled";
 
                clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
                resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
                reset-names = "axi", "ahb", "dclk";
+               power-domains = <&power RK3399_PD_VOPB>;
                iommus = <&vopb_mmu>;
                status = "disabled";
 
                                rockchip,pins =
                                        <4 21 RK_FUNC_1 &pcfg_pull_none>;
                        };
+
+                       spdif_bus_1: spdif-bus-1 {
+                               rockchip,pins =
+                                       <3 16 RK_FUNC_3 &pcfg_pull_none>;
+                       };
                };
 
                spi0 {