reg = <0x0 0x0>;
enable-method = "psci";
#cooling-cells = <2>; /* min followed by max */
+ dynamic-power-coefficient = <121>;
clocks = <&cru ARMCLKL>;
cpu-idle-states = <&cpu_sleep>;
operating-points-v2 = <&cluster0_opp>;
+ sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
};
cpu_l1: cpu@1 {
clocks = <&cru ARMCLKL>;
cpu-idle-states = <&cpu_sleep>;
operating-points-v2 = <&cluster0_opp>;
+ sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
};
cpu_l2: cpu@2 {
clocks = <&cru ARMCLKL>;
cpu-idle-states = <&cpu_sleep>;
operating-points-v2 = <&cluster0_opp>;
+ sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
};
cpu_l3: cpu@3 {
clocks = <&cru ARMCLKL>;
cpu-idle-states = <&cpu_sleep>;
operating-points-v2 = <&cluster0_opp>;
+ sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
};
cpu_b0: cpu@100 {
reg = <0x0 0x100>;
enable-method = "psci";
#cooling-cells = <2>; /* min followed by max */
+ dynamic-power-coefficient = <1068>;
clocks = <&cru ARMCLKB>;
cpu-idle-states = <&cpu_sleep>;
operating-points-v2 = <&cluster1_opp>;
+ sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
};
cpu_b1: cpu@101 {
clocks = <&cru ARMCLKB>;
cpu-idle-states = <&cpu_sleep>;
operating-points-v2 = <&cluster1_opp>;
+ sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
};
idle-states {
min-residency-us = <1150>;
};
};
+
+ /include/ "rk3399-sched-energy.dtsi"
+
};
cluster0_opp: opp_table0 {
#size-cells = <2>;
ranges;
status = "disabled";
- usbdrd_dwc3_0: dwc3 {
+ usbdrd_dwc3_0: dwc3@fe800000 {
compatible = "snps,dwc3";
reg = <0x0 0xfe800000 0x0 0x100000>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "otg";
- tx-fifo-resize;
snps,dis_enblslpm_quirk;
snps,phyif_utmi_16_bits;
snps,dis_u2_freeclk_exists_quirk;
#size-cells = <2>;
ranges;
status = "disabled";
- usbdrd_dwc3_1: dwc3 {
+ usbdrd_dwc3_1: dwc3@fe900000 {
compatible = "snps,dwc3";
reg = <0x0 0xfe900000 0x0 0x100000>;
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "otg";
- tx-fifo-resize;
snps,dis_enblslpm_quirk;
snps,phyif_utmi_16_bits;
snps,dis_u2_freeclk_exists_quirk;
};
thermal-zones {
- cpu {
+ soc_thermal: soc-thermal {
polling-delay-passive = <100>; /* milliseconds */
polling-delay = <1000>; /* milliseconds */
+ sustainable-power = <2600>; /* milliwatts */
thermal-sensors = <&tsadc 0>;
trips {
- cpu_alert0: cpu_alert0 {
+ threshold: trip-point@0 {
temperature = <70000>; /* millicelsius */
hysteresis = <2000>; /* millicelsius */
type = "passive";
};
- cpu_alert1: cpu_alert1 {
- temperature = <75000>; /* millicelsius */
+ target: trip-point@1 {
+ temperature = <85000>; /* millicelsius */
hysteresis = <2000>; /* millicelsius */
type = "passive";
};
- cpu_crit: cpu_crit {
+ soc_crit: soc-crit {
temperature = <95000>; /* millicelsius */
hysteresis = <2000>; /* millicelsius */
type = "critical";
cooling-maps {
map0 {
- trip = <&cpu_alert0>;
+ trip = <&target>;
cooling-device =
- <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
- trip = <&cpu_alert1>;
+ trip = <&target>;
cooling-device =
- <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
+ map2 {
+ trip = <&target>;
+ cooling-device =
+ <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
};
};
- gpu {
+ gpu_thermal: gpu-thermal {
polling-delay-passive = <100>; /* milliseconds */
polling-delay = <1000>; /* milliseconds */
thermal-sensors = <&tsadc 1>;
-
- trips {
- gpu_alert0: gpu_alert0 {
- temperature = <75000>; /* millicelsius */
- hysteresis = <2000>; /* millicelsius */
- type = "passive";
- };
- gpu_crit: gpu_crit {
- temperature = <95000>; /* millicelsius */
- hysteresis = <2000>; /* millicelsius */
- type = "critical";
- };
- };
-
- cooling-maps {
- map0 {
- trip = <&gpu_alert0>;
- cooling-device =
- <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
- };
};
};
reg = <0x0 0xff310000 0x0 0x1000>;
power: power-controller {
- status = "disabled";
+ status = "okay";
compatible = "rockchip,rk3399-power-controller";
#power-domain-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
- pd_center {
- reg = <RK3399_PD_CENTER>;
- #address-cells = <1>;
- #size-cells = <0>;
- pd_vdu {
- reg = <RK3399_PD_VDU>;
- pm_qos = <&qos_video_m1_r>,
- <&qos_video_m1_w>;
- };
- pd_vcodec {
- reg = <RK3399_PD_VCODEC>;
- pm_qos = <&qos_video_m0>;
- };
- pd_iep {
- reg = <RK3399_PD_IEP>;
- pm_qos = <&qos_iep>;
- };
- pd_rga {
- reg = <RK3399_PD_RGA>;
- pm_qos = <&qos_rga_r>,
- <&qos_rga_w>;
- };
+ pd_vdu {
+ reg = <RK3399_PD_VDU>;
+ pm_qos = <&qos_video_m1_r>,
+ <&qos_video_m1_w>;
+ };
+ pd_vcodec {
+ reg = <RK3399_PD_VCODEC>;
+ pm_qos = <&qos_video_m0>;
+ };
+ pd_iep {
+ reg = <RK3399_PD_IEP>;
+ pm_qos = <&qos_iep>;
+ };
+ pd_rga {
+ reg = <RK3399_PD_RGA>;
+ pm_qos = <&qos_rga_r>,
+ <&qos_rga_w>;
};
pd_vio {
reg = <RK3399_PD_VIO>;
assigned-clock-rates =
<400000000>, <200000000>,
<400000000>, <200000000>,
- <816000000>, <1008000000>,
+ <816000000>, <816000000>,
<594000000>, <800000000>,
<1000000000>,
<150000000>, <75000000>,
clock-names = "clk_mali";
#cooling-cells = <2>; /* min followed by max */
operating-points-v2 = <&gpu_opp_table>;
-
+ power-domains = <&power RK3399_PD_GPU>;
status = "disabled";
power_model {
compatible = "arm,mali-simple-power-model";
voltage = <900>;
frequency = <500>;
- static-power = <500>;
- dynamic-power = <1500>;
- ts = <20000 2000 (-20) 2>;
- thermal-zone = "gpu";
+ static-power = <300>;
+ dynamic-power = <1780>;
+ ts = <32000 4700 (-80) 2>;
+ thermal-zone = "gpu-thermal";
};
};
projects / firefly-linux-kernel-4.4.55.git / blobdiff