* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
-#include <dt-bindings/display/rk_fb.h>
-#include <dt-bindings/display/mipi_dsi.h>
+
+#include <dt-bindings/display/drm_mipi_dsi.h>
+#include <dt-bindings/display/media-bus-format.h>
+#include "rk3399-vop-clk-set.dtsi"
/ {
compatible = "rockchip,android", "rockchip,rk3399";
chosen {
- bootargs = "console=uart,mmio32,0xff1a0000";
+ bootargs = "earlycon=uart8250,mmio32,0xff1a0000 swiotlb=1";
};
ramoops_mem: ramoops_mem {
- reg = <0x0 0x100000 0x0 0x100000>;
+ reg = <0x0 0x110000 0x0 0xf0000>;
reg-names = "ramoops_mem";
};
compatible = "ramoops";
record-size = <0x0 0x20000>;
console-size = <0x0 0x80000>;
- ftrace-size = <0x0 0x10000>;
+ ftrace-size = <0x0 0x00000>;
pmsg-size = <0x0 0x50000>;
memory-region = <&ramoops_mem>;
};
+ fiq_debugger: fiq-debugger {
+ compatible = "rockchip,fiq-debugger";
+ rockchip,serial-id = <2>;
+ rockchip,signal-irq = <182>;
+ rockchip,wake-irq = <0>;
+ rockchip,irq-mode-enable = <1>; /* If enable uart uses irq instead of fiq */
+ rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2c_xfer>;
+ };
+
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
- /* global autoconfigured region for contiguous allocations */
- linux,cma {
- compatible = "shared-dma-pool";
- reusable;
- size = <0x0 0x8000000>;
- linux,cma-default;
- };
- };
-
- ion {
- compatible = "rockchip,ion";
- #address-cells = <1>;
- #size-cells = <0>;
-
- cma-heap {
- reg = <0x00000000 0x02000000>;
- };
-
- system-heap {
+ drm_logo: drm-logo@00000000 {
+ compatible = "rockchip,drm-logo";
+ reg = <0x0 0x0 0x0 0x0>;
};
};
};
};
- vpu: vpu_service@ff650000 {
- compatible = "rockchip,vpu_service";
- rockchip,grf = <&grf>;
- iommu_enabled = <1>;
- reg = <0x0 0xff650000 0x0 0x800>;
- interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "irq_dec", "irq_enc";
- clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
- clock-names = "aclk_vcodec", "hclk_vcodec";
- resets = <&cru SRST_H_VCODEC>, <&cru SRST_A_VCODEC>;
- reset-names = "video_h", "video_a";
- power-domains = <&power RK3399_PD_VCODEC>;
- name = "vpu_service";
- dev_mode = <0>;
- };
-
- vpu_mmu: vpu_mmu {
- dbgname = "vpu";
- compatible = "rockchip,vpu_mmu";
- reg = <0x0 0xff650800 0x0 0x40>;
- interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "vpu_mmu";
- };
-
- rkvdec: rkvdec@ff660000 {
- compatible = "rockchip,rkvdec";
- rockchip,grf = <&grf>;
- iommu_enabled = <1>;
- reg = <0x0 0xff660000 0x0 0x400>;
- interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "irq_dec";
- clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>,<&cru SCLK_VDU_CA>,<&cru SCLK_VDU_CORE>;
- clock-names = "aclk_vcodec", "hclk_vcodec", "clk_cabac", "clk_core";
- resets = <&cru SRST_H_VDU>, <&cru SRST_A_VDU>;
- reset-names = "video_h", "video_a";
- power-domains = <&power RK3399_PD_VDU>;
- dev_mode = <2>;
- name = "rkvdec";
- };
-
- vdec_mmu: vdec_mmu {
- dbgname = "vdec";
- compatible = "rockchip,vdec_mmu";
- reg = <0x0 0xff660480 0x0 0x40>,
- <0x0 0xff6604c0 0x0 0x40>;
- interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "vdec_mmu";
- };
-
- iep: iep@ff670000 {
- compatible = "rockchip,iep";
- iommu_enabled = <1>;
- reg = <0x0 0xff670000 0x0 0x800>;
- interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
- clock-names = "aclk_iep", "hclk_iep";
- power-domains = <&power RK3399_PD_IEP>;
- version = <2>;
- };
-
- iep_mmu: iep-mmu {
- dbgname = "iep";
- compatible = "rockchip,iep_mmu";
- reg = <0x0 0xff670800 0x0 0x40>;
- interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "iep_mmu";
- };
-
rga: rga@ff680000 {
compatible = "rockchip,rga2";
dev_mode = <1>;
reg = <0x0 0xff680000 0x0 0x1000>;
- interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
clock-names = "aclk_rga", "hclk_rga", "clk_rga";
power-domains = <&power RK3399_PD_RGA>;
+ dma-coherent;
status = "okay";
};
- fb: fb {
- status = "okay";
- compatible = "rockchip,rk-fb";
- rockchip,disp-mode = <DUAL>;
- };
-
- rk_screen: screen {
- status = "okay";
- compatible = "rockchip,screen";
+ isp0: isp@ff910000 {
+ compatible = "rockchip,rk3399-isp", "rockchip,isp";
+ reg = <0x0 0xff910000 0x0 0x4000>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks =
+ <&cru SCLK_CIF_OUT>, <&cru SCLK_CIF_OUT>,
+ <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru SCLK_MIPIDPHY_REF>,
+ <&cru ACLK_ISP0_NOC>, <&cru ACLK_ISP0_WRAPPER>,
+ <&cru HCLK_ISP0_NOC>, <&cru HCLK_ISP0_WRAPPER>,
+ <&cru SCLK_ISP0>, <&cru SCLK_DPHY_RX0_CFG>;
+ clock-names =
+ "clk_cif_out", "clk_cif_pll",
+ "pclk_dphytxrx", "pclk_dphy_ref",
+ "aclk_isp0_noc", "aclk_isp0_wrapper",
+ "hclk_isp0_noc", "hclk_isp0_wrapper",
+ "clk_isp0", "pclk_dphyrx";
+ pinctrl-names =
+ "cif_clkout", "isp_dvp8bit0", "isp_mipi_fl",
+ "isp_mipi_fl_prefl", "isp_flash_as_gpio",
+ "isp_flash_as_trigger_out";
+ pinctrl-0 = <&cif_clkout>;
+ pinctrl-1 = <&isp_dvp_d0d7>;
+ pinctrl-2 = <&cif_clkout>;
+ pinctrl-3 = <&isp_prelight>;
+ pinctrl-4 = <&isp_flash_trigger_as_gpio>;
+ pinctrl-5 = <&isp_flash_trigger>;
+ rockchip,isp,mipiphy = <2>;
+ rockchip,isp,cifphy = <1>;
+ rockchip,isp,dsiphy,reg = <0xff968000 0x8000>;
+ rockchip,grf = <&grf>;
+ rockchip,cru = <&cru>;
+ rockchip,gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
+ rockchip,isp,iommu-enable = <1>;
+ power-domains = <&power RK3399_PD_ISP0>;
+ iommus = <&isp0_mmu>;
+ status = "disabled";
};
- vopb_rk_fb: vop-rk-fb@ff900000 {
- status = "disabled";
- compatible = "rockchip,rk3399-lcdc";
- rockchip,prop = <PRMRY>;
- reg = <0x0 0xff900000 0x0 0x3efc>;
- interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
- clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
- resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
- reset-names = "axi", "ahb", "dclk";
+ isp1: isp@ff920000 {
+ compatible = "rockchip,rk3399-isp", "rockchip,isp";
+ reg = <0x0 0xff920000 0x0 0x4000>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks =
+ <&cru ACLK_ISP1_NOC>, <&cru ACLK_ISP1_WRAPPER>,
+ <&cru HCLK_ISP1_NOC>, <&cru HCLK_ISP1_WRAPPER>,
+ <&cru SCLK_ISP1>, <&cru SCLK_CIF_OUT>,
+ <&cru SCLK_CIF_OUT>, <&cru SCLK_DPHY_TX1RX1_CFG>,
+ <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_ISP1_WRAPPER>,
+ <&cru SCLK_DPHY_RX0_CFG>, <&cru PCLK_MIPI_DSI1>,
+ <&cru SCLK_MIPIDPHY_CFG>;
+ clock-names =
+ "aclk_isp1_noc", "aclk_isp1_wrapper",
+ "hclk_isp1_noc", "hclk_isp1_wrapper",
+ "clk_isp1", "clk_cif_out",
+ "clk_cif_pll", "pclk_dphytxrx",
+ "pclk_dphy_ref", "pclk_isp1",
+ "pclk_dphyrx", "pclk_mipi_dsi",
+ "mipi_dphy_cfg";
+ pinctrl-names =
+ "cif_clkout", "isp_dvp8bit0", "isp_mipi_fl",
+ "isp_mipi_fl_prefl", "isp_flash_as_gpio",
+ "isp_flash_as_trigger_out";
+ pinctrl-0 = <&cif_clkout>;
+ pinctrl-1 = <&isp_dvp_d0d7>;
+ pinctrl-2 = <&cif_clkout>;
+ pinctrl-3 = <&isp_prelight>;
+ pinctrl-4 = <&isp_flash_trigger_as_gpio>;
+ pinctrl-5 = <&isp_flash_trigger>;
+ rockchip,isp,mipiphy = <2>;
+ rockchip,isp,cifphy = <1>;
+ rockchip,isp,dsiphy,reg = <0xff968000 0x8000>;
rockchip,grf = <&grf>;
- rockchip,pwr18 = <0>;
- rockchip,iommu-enabled = <1>;
- power-domains = <&power RK3399_PD_VOPB>;
+ rockchip,cru = <&cru>;
+ rockchip,gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
+ rockchip,isp,iommu-enable = <1>;
+ power-domains = <&power RK3399_PD_ISP1>;
+ iommus = <&isp1_mmu>;
+ status = "disabled";
};
- vopb_mmu_rk_fb: vopb-mmu {
- status = "okay";
- dbgname = "vop";
- compatible = "rockchip,vopb_mmu";
- reg = <0x0 0xff903f00 0x0 0x100>;
- interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "vopb_mmu";
+ uboot-charge {
+ compatible = "rockchip,uboot-charge";
+ rockchip,uboot-charge-on = <1>;
+ rockchip,android-charge-on = <0>;
};
- vopl_rk_fb: vop-rk-fb@ff8f0000 {
+ hdmi_dp_sound: hdmi-dp-sound {
status = "disabled";
- compatible = "rockchip,rk3399-lcdc";
- rockchip,prop = <EXTEND>;
- reg = <0x0 0xff8f0000 0x0 0x3efc>;
- interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
- clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
- resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
- reset-names = "axi", "ahb", "dclk";
- rockchip,grf = <&grf>;
- rockchip,pwr18 = <0>;
- rockchip,iommu-enabled = <1>;
- power-domains = <&power RK3399_PD_VOPL>;
+ compatible = "rockchip,rk3399-hdmi-dp";
+ rockchip,cpu = <&i2s2>;
+ rockchip,codec = <&hdmi>, <&cdn_dp>;
};
+};
- vopl_mmu_rk_fb: vopl-mmu {
- status = "okay";
- dbgname = "vop";
- compatible = "rockchip,vopl_mmu";
- reg = <0x0 0xff8f3f00 0x0 0x100>;
- interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "vopl_mmu";
- };
+&vopb {
+ status = "okay";
+};
- hdmi_rk_fb: hdmi-rk-fb@ff940000 {
- status = "disabled";
- compatible = "rockchip,rk3399-hdmi";
- reg = <0x0 0xff940000 0x0 0x20000>;
- interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_HDMI_CTRL>,
- <&cru HCLK_HDCP>,
- <&cru SCLK_HDMI_CEC>,
- <&cru PLL_VPLL>,
- <&cru SCLK_HDMI_SFR>;
- clock-names = "pclk_hdmi",
- "hdcp_clk_hdmi",
- "cec_clk_hdmi",
- "dclk_hdmi_phy",
- "sclk_hdmi_sfr";
- resets = <&cru SRST_HDMI_CTRL>;
- reset-names = "hdmi";
- pinctrl-names = "default", "gpio";
- pinctrl-0 = <&hdmi_i2c_xfer &hdmi_cec>;
- pinctrl-1 = <&i2c3_gpio>;
- rockchip,grf = <&grf>;
- power-domains = <&power RK3399_PD_HDCP>;
- };
+&vopb_mmu {
+ status = "okay";
+};
- mipi0_rk_fb: mipi-rk-fb@ff960000 {
- compatible = "rockchip,rk3399-dsi";
- rockchip,prop = <0>;
- rockchip,grf = <&grf>;
- reg = <0x0 0xff960000 0x0 0x8000>;
- interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>, <&cru SCLK_MIPIDPHY_CFG>;
- clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "mipi_dphy_cfg";
- power-domains = <&power RK3399_PD_VIO>;
- status = "disabled";
- };
+&vopl {
+ status = "okay";
+};
- mipi1_rk_fb: mipi-rk-fb@ff968000 {
- compatible = "rockchip,rk3399-dsi";
- rockchip,prop = <1>;
- rockchip,grf = <&grf>;
- reg = <0x0 0xff968000 0x0 0x8000>;
- interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI1>, <&cru SCLK_MIPIDPHY_CFG>;
- clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "mipi_dphy_cfg";
- power-domains = <&power RK3399_PD_VIO>;
- status = "disabled";
- };
+&vopl_mmu {
+ status = "okay";
+};
- edp_rk_fb: edp-rk-fb@ff970000 {
- compatible = "rockchip,rk3399-edp-fb";
- reg = <0x0 0xff970000 0x0 0x8000>;
- rockchip,grf = <&grf>;
- interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
- clock-names = "clk_edp", "pclk_edp";
- resets = <&cru SRST_P_EDP_CTRL>;
- reset-names = "edp_apb";
- status = "disabled";
- };
+&hdmi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #sound-dai-cells = <0>;
+ ddc-i2c-scl-high-time-ns = <9625>;
+ ddc-i2c-scl-low-time-ns = <10000>;
+ status = "okay";
+};
- hdmi_sound: hdmi-sound {
- status = "disabled";
- compatible = "simple-audio-card";
- simple-audio-card,format = "i2s";
- simple-audio-card,mclk-fs = <256>;
- simple-audio-card,name = "rockchip,hdmi";
- simple-audio-card,cpu {
- sound-dai = <&i2s2>;
+&display_subsystem {
+ status = "okay";
+
+ ports = <&vopb_out>, <&vopl_out>;
+ memory-region = <&drm_logo>;
+ route {
+ route_hdmi: route-hdmi {
+ status = "disabled";
+ logo,uboot = "logo.bmp";
+ logo,kernel = "logo_kernel.bmp";
+ logo,mode = "fullscreen";
+ charge_logo,mode = "center";
+ connect = <&vopb_out_hdmi>;
};
- simple-audio-card,codec {
- sound-dai = <&dw_hdmi_audio>;
+
+ route_mipi: route-mipi {
+ status = "disabled";
+ logo,uboot = "logo.bmp";
+ logo,kernel = "logo_kernel.bmp";
+ logo,mode = "fullscreen";
+ charge_logo,mode = "center";
+ connect = <&vopb_out_mipi>;
};
- };
- dw_hdmi_audio: dw-hdmi-audio {
- status = "disabled";
- compatible = "rockchip,dw-hdmi-audio";
- #sound-dai-cells = <0>;
+ route_edp: route-edp {
+ status = "disabled";
+ logo,uboot = "logo.bmp";
+ logo,kernel = "logo_kernel.bmp";
+ logo,mode = "fullscreen";
+ charge_logo,mode = "center";
+ connect = <&vopb_out_edp>;
+ };
};
};
#sound-dai-cells = <0>;
};
+&rkvdec {
+ status = "okay";
+};
+
&usbdrd_dwc3_0 {
- dr_mode = "peripheral";
+ dr_mode = "otg";
};
+
+&vpu {
+ status = "okay";
+};
+
+&pinctrl {
+ isp {
+ cif_clkout: cif-clkout {
+ rockchip,pins =
+ /*cif_clkout*/
+ <2 11 RK_FUNC_3 &pcfg_pull_none>;
+ };
+
+ isp_dvp_d0d7: isp-dvp-d0d7 {
+ rockchip,pins =
+ /*cif_data0*/
+ <2 0 RK_FUNC_3 &pcfg_pull_none>,
+ /*cif_data1*/
+ <2 1 RK_FUNC_3 &pcfg_pull_none>,
+ /*cif_data2*/
+ <2 2 RK_FUNC_3 &pcfg_pull_none>,
+ /*cif_data3*/
+ <2 3 RK_FUNC_3 &pcfg_pull_none>,
+ /*cif_data4*/
+ <2 4 RK_FUNC_3 &pcfg_pull_none>,
+ /*cif_data5*/
+ <2 5 RK_FUNC_3 &pcfg_pull_none>,
+ /*cif_data6*/
+ <2 6 RK_FUNC_3 &pcfg_pull_none>,
+ /*cif_data7*/
+ <2 7 RK_FUNC_3 &pcfg_pull_none>,
+ /*cif_sync*/
+ <2 8 RK_FUNC_3 &pcfg_pull_none>,
+ /*cif_href*/
+ <2 9 RK_FUNC_3 &pcfg_pull_none>,
+ /*cif_clkin*/
+ <2 10 RK_FUNC_3 &pcfg_pull_none>;
+ };
+
+ isp_shutter: isp-shutter {
+ rockchip,pins =
+ /*SHUTTEREN*/
+ <1 1 RK_FUNC_1 &pcfg_pull_none>,
+ /*SHUTTERTRIG*/
+ <1 0 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ isp_flash_trigger: isp-flash-trigger {
+ /*ISP_FLASHTRIGOU*/
+ rockchip,pins = <1 3 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ isp_prelight: isp-prelight {
+ /*ISP_PRELIGHTTRIG*/
+ rockchip,pins = <1 4 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
+ /*ISP_FLASHTRIGOU*/
+ rockchip,pins =
+ <0 17 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
projects / firefly-linux-kernel-4.4.55.git / blobdiff