arm64: dts: rockchip: add allocator type inside vpu & rkvdec for rk3399-android

[firefly-linux-kernel-4.4.55.git] / arch / arm64 / boot / dts / rockchip / rk3399-android.dtsi

diff --git a/arch/arm64/boot/dts/rockchip/rk3399-android.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-android.dtsi
index a88b8945b9080e8cc59f915b4d076e7ea70fb590..720a902c10060ee9a76caf1e1d1f331ceecb480f 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3399-android.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-android.dtsi
@@ -55,7 +55,7 @@
        };
 
        ramoops_mem: ramoops_mem {
-               reg = <0x0 0x100000 0x0 0x100000>;
+               reg = <0x0 0x110000 0x0 0xf0000>;
                reg-names = "ramoops_mem";
        };
 
@@ -63,7 +63,7 @@
                compatible = "ramoops";
                record-size = <0x0 0x20000>;
                console-size = <0x0 0x80000>;
-               ftrace-size = <0x0 0x10000>;
+               ftrace-size = <0x0 0x00000>;
                pmsg-size = <0x0 0x50000>;
                memory-region = <&ramoops_mem>;
        };
@@ -167,14 +167,15 @@
                reg = <0x0 0xfec00000 0x0 0x100000>;
                interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
-                        <&cru SCLK_SPDIF_REC_DPTX>;
-               clock-names = "core-clk", "pclk", "spdif";
+                        <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
+               clock-names = "core-clk", "pclk", "spdif", "grf";
                assigned-clocks = <&cru SCLK_DP_CORE>;
                assigned-clock-rates = <100000000>;
                power-domains = <&power RK3399_PD_HDCP>;
-               phys = <&tcphy0 0>, <&tcphy1 0>;
-               resets = <&cru SRST_DPTX_SPDIF_REC>;
-               reset-names = "spdif";
+               phys = <&tcphy0_dp>, <&tcphy1_dp>;
+               resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>,
+                        <&cru SRST_P_UPHY0_APB>;
+               reset-names = "spdif", "dptx", "apb";
                rockchip,grf = <&grf>;
                #address-cells = <1>;
                #size-cells = <0>;
@@ -200,17 +201,6 @@
                                sound-dai = <&cdn_dp_fb 0>;
                        };
                };
-
-               simple-audio-card,dai-link@1 {
-                       format = "spdif";
-                       cpu {
-                               sound-dai = <&spdif>;
-                       };
-
-                       codec {
-                               sound-dai = <&cdn_dp_fb 1>;
-                       };
-               };
        };
 
        vpu: vpu_service@ff650000 {
@@ -228,6 +218,8 @@
                power-domains = <&power RK3399_PD_VCODEC>;
                name = "vpu_service";
                dev_mode = <0>;
+               /* 0 means ion, 1 means drm */
+               allocator = <0>;
        };
 
        vpu_mmu: vpu_mmu {
@@ -252,6 +244,8 @@
                power-domains = <&power RK3399_PD_VDU>;
                dev_mode = <2>;
                name = "rkvdec";
+               /* 0 means ion, 1 means drm */
+               allocator = <0>;
        };
 
        vdec_mmu: vdec_mmu {
@@ -320,6 +314,7 @@
                rockchip,pwr18 = <0>;
                rockchip,iommu-enabled = <1>;
                power-domains = <&power RK3399_PD_VOPB>;
+               devfreq = <&dmc>;
        };
 
        vopb_mmu_rk_fb: vopb-mmu {
@@ -345,6 +340,7 @@
                rockchip,pwr18 = <0>;
                rockchip,iommu-enabled = <1>;
                power-domains = <&power RK3399_PD_VOPL>;
+               devfreq = <&dmc>;
        };
 
        vopl_mmu_rk_fb: vopl-mmu {
@@ -356,6 +352,29 @@
                interrupt-names = "vopl_mmu";
        };
 
+       cif_isp0: cif_isp@ff910000 {
+               compatible = "rockchip,rk3399-cif-isp";
+               rockchip,grf = <&grf>;
+               reg = <0x0 0xff910000 0x0 0x10000>, <0x0 0xff968000 0x0 0x8000>;
+               reg-names = "register", "dsihost-register";
+               clocks =
+                       <&cru SCLK_CIF_OUT>, <&cru SCLK_CIF_OUT>,
+                       <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru SCLK_MIPIDPHY_REF>,
+                       <&cru ACLK_ISP0_NOC>, <&cru ACLK_ISP0_WRAPPER>,
+                       <&cru HCLK_ISP0_NOC>, <&cru HCLK_ISP0_WRAPPER>,
+                       <&cru SCLK_ISP0>, <&cru SCLK_DPHY_RX0_CFG>;
+               clock-names =
+                       "clk_cif_out", "clk_cif_pll",
+                       "pclk_dphytxrx", "pclk_dphy_ref",
+                       "aclk_isp0_noc", "aclk_isp0_wrapper",
+                       "hclk_isp0_noc", "hclk_isp0_wrapper",
+                       "clk_isp0", "pclk_dphyrx";
+               interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
+               interrupt-names = "cif_isp10_irq";
+               power-domains = <&power RK3399_PD_ISP0>;
+               status = "disabled";
+       };
+
        isp0: isp@ff910000 {
                compatible = "rockchip,rk3399-isp", "rockchip,isp";
                reg = <0x0 0xff910000 0x0 0x10000>;
@@ -506,11 +525,12 @@
                reg = <0x0 0xff970000 0x0 0x8000>;
                rockchip,grf = <&grf>;
                interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
-               clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
-               clock-names = "clk_edp", "pclk_edp";
+               clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>, <&cru PCLK_VIO_GRF>;
+               clock-names = "clk_edp", "pclk_edp", "clk_grf";
                resets = <&cru SRST_P_EDP_CTRL>;
                reset-names = "edp_apb";
                status = "disabled";
+               power-domains = <&power RK3399_PD_EDP>;
        };
 };
 
@@ -571,4 +591,15 @@
                        rockchip,pins = <0 17 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
+
+       cam_pins {
+               cam0_default_pins: cam0-default-pins {
+                       rockchip,pins = <4 27 RK_FUNC_GPIO &pcfg_pull_none>,
+                                       <2 11 RK_FUNC_3 &pcfg_pull_none>;
+               };
+               cam0_sleep_pins: cam0-sleep-pins {
+                       rockchip,pins = <4 27 RK_FUNC_3 &pcfg_pull_none>,
+                                       <2 11 RK_FUNC_GPIO &pcfg_pull_none>;
+               };
+       };
 };